Lines Matching refs:job
90 store_general(struct vc5_job *job,
116 ((job->cleared & pipe_bit) &&
152 (job->cleared & pipe_bit)));
154 !(job->cleared & PIPE_CLEAR_DEPTH);
156 !(job->cleared & PIPE_CLEAR_STENCIL);
197 vc5_rcl_emit_loads(struct vc5_job *job, struct vc5_cl *cl)
199 uint32_t read_but_not_cleared = job->resolve & ~job->cleared;
206 struct pipe_surface *psurf = job->cbufs[i];
221 (job->zsbuf && job->zsbuf->texture->nr_samples > 1))) {
222 load_general(cl, job->zsbuf,
252 vc5_rcl_emit_stores(struct vc5_job *job, struct vc5_cl *cl)
254 MAYBE_UNUSED bool needs_color_clear = job->cleared & PIPE_CLEAR_COLOR_BUFFERS;
255 MAYBE_UNUSED bool needs_z_clear = job->cleared & PIPE_CLEAR_DEPTH;
256 MAYBE_UNUSED bool needs_s_clear = job->cleared & PIPE_CLEAR_STENCIL;
273 (job->cleared & PIPE_CLEAR_COLOR_BUFFERS) ==
274 (job->resolve & PIPE_CLEAR_COLOR_BUFFERS));
276 uint32_t stores_pending = job->resolve;
289 if (!(job->resolve & bit))
292 struct pipe_surface *psurf = job->cbufs[i];
299 store_general(job, cl, psurf, RENDER_TARGET_0 + i, bit,
305 if (job->resolve & PIPE_CLEAR_DEPTHSTENCIL && job->zsbuf &&
306 !(V3D_VERSION < 40 && job->zsbuf->texture->nr_samples <= 1)) {
309 struct vc5_resource *rsc = vc5_resource(job->zsbuf->texture);
311 if (job->resolve & PIPE_CLEAR_DEPTH) {
312 store_general(job, cl, job->zsbuf, Z,
317 if (job->resolve & PIPE_CLEAR_STENCIL) {
318 store_general(job, cl, job->zsbuf, STENCIL,
324 store_general(job, cl, job->zsbuf,
325 zs_buffer_from_pipe_bits(job->resolve),
326 job->resolve & PIPE_CLEAR_DEPTHSTENCIL,
374 vc5_rcl_emit_generic_per_tile_list(struct vc5_job *job, int last_cbuf)
379 struct vc5_cl *cl = &job->indirect;
390 vc5_rcl_emit_loads(job, cl);
409 vc5_rcl_emit_stores(job, cl);
417 cl_emit(&job->rcl, START_ADDRESS_OF_GENERIC_TILE_LIST, branch) {
425 v3d_setup_render_target(struct vc5_job *job, int cbuf,
428 if (!job->cbufs[cbuf])
431 struct vc5_surface *surf = vc5_surface(job->cbufs[cbuf]);
441 v3dX(emit_rcl)(struct vc5_job *job)
444 assert(!job->rcl.bo);
446 vc5_cl_ensure_space_with_branch(&job->rcl, 200 + 256 *
448 job->submit.rcl_start = job->rcl.bo->offset;
449 vc5_job_add_bo(job, job->rcl.bo);
453 if (job->cbufs[i])
461 cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_COMMON_CONFIGURATION,
464 config.enable_z_store = job->resolve & PIPE_CLEAR_DEPTH;
465 config.enable_stencil_store = job->resolve & PIPE_CLEAR_STENCIL;
467 if (job->zsbuf) {
468 struct vc5_surface *surf = vc5_surface(job->zsbuf);
475 config.early_z_disable = !job->uses_early_z;
477 config.image_width_pixels = job->draw_width;
478 config.image_height_pixels = job->draw_height;
483 config.multisample_mode_4x = job->msaa;
485 config.maximum_bpp_of_all_render_targets = job->internal_bpp;
489 struct pipe_surface *psurf = job->cbufs[i];
502 uint32_t implicit_padded_height = (align(job->draw_height, uif_block_height) /
515 cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_RENDER_TARGET_CONFIG, rt) {
524 if (job->resolve & PIPE_CLEAR_COLOR0 << i)
529 cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_CLEAR_COLORS_PART1,
531 clear.clear_color_low_32_bits = job->clear_color[i][0];
532 clear.clear_color_next_24_bits = job->clear_color[i][1] & 0xffffff;
537 cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_CLEAR_COLORS_PART2,
540 ((job->clear_color[i][1] >> 24) |
541 (job->clear_color[i][2] << 8));
543 ((job->clear_color[i][2] >> 24) |
544 ((job->clear_color[i][3] & 0xffff) << 8));
550 cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_CLEAR_COLORS_PART3,
553 clear.clear_color_high_16_bits = job->clear_color[i][3] >> 16;
560 cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_RENDER_TARGET_CONFIG, rt) {
561 v3d_setup_render_target(job, 0,
565 v3d_setup_render_target(job, 1,
569 v3d_setup_render_target(job, 2,
573 v3d_setup_render_target(job, 3,
582 if (job->zsbuf) {
583 struct pipe_surface *psurf = job->zsbuf;
587 cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_Z_STENCIL_CONFIG, zs) {
599 if (job->resolve & PIPE_CLEAR_DEPTHSTENCIL)
607 cl_emit(&job->rcl,
627 cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_Z_STENCIL_CLEAR_VALUES,
629 clear.z_clear_value = job->clear_z;
630 clear.stencil_vg_mask_clear_value = job->clear_s;
636 cl_emit(&job->rcl, TILE_LIST_INITIAL_BLOCK_SIZE, init) {
647 cl_emit(&job->rcl, MULTICORE_RENDERING_TILE_LIST_SET_BASE, list) {
648 list.address = cl_address(job->tile_alloc, 0);
651 cl_emit(&job->rcl, MULTICORE_RENDERING_SUPERTILE_CONFIGURATION, config) {
657 frame_w_in_supertiles = div_round_up(job->draw_tiles_x,
659 frame_h_in_supertiles = div_round_up(job->draw_tiles_y,
672 config.total_frame_width_in_tiles = job->draw_tiles_x;
673 config.total_frame_height_in_tiles = job->draw_tiles_y;
683 cl_emit(&job->rcl, TILE_COORDINATES, coords) {
689 cl_emit(&job->rcl, STORE_TILE_BUFFER_GENERAL, store) {
693 cl_emit(&job->rcl, END_OF_LOADS, end);
694 cl_emit(&job->rcl, STORE_TILE_BUFFER_GENERAL, store) {
697 cl_emit(&job->rcl, CLEAR_TILE_BUFFERS, clear) {
701 cl_emit(&job->rcl, END_OF_TILE_MARKER, end);
704 cl_emit(&job->rcl, FLUSH_VCD_CACHE, flush);
706 vc5_rcl_emit_generic_per_tile_list(job, nr_cbufs - 1);
708 cl_emit(&job->rcl, WAIT_ON_SEMAPHORE, sem);
711 uint32_t supertile_w_in_pixels = job->tile_width * supertile_w;
712 uint32_t supertile_h_in_pixels = job->tile_height * supertile_h;
713 uint32_t min_x_supertile = job->draw_min_x / supertile_w_in_pixels;
714 uint32_t min_y_supertile = job->draw_min_y / supertile_h_in_pixels;
715 uint32_t max_x_supertile = (job->draw_max_x - 1) / supertile_w_in_pixels;
716 uint32_t max_y_supertile = (job->draw_max_y - 1) / supertile_h_in_pixels;
720 cl_emit(&job->rcl, SUPERTILE_COORDINATES, coords) {
727 cl_emit(&job->rcl, END_OF_RENDERING, end);
