Lines Matching defs:ARMBaseInstrInfo
1 //===- ARMBaseInstrInfo.cpp - ARM Instruction Information -------*- C++ -*-===//
14 #include "ARMBaseInstrInfo.h"
85 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
98 ScheduleHazardRecognizer *ARMBaseInstrInfo::
108 ScheduleHazardRecognizer *ARMBaseInstrInfo::
118 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
270 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
369 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
398 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
436 bool ARMBaseInstrInfo::
443 bool ARMBaseInstrInfo::
464 bool ARMBaseInstrInfo::
491 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
513 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
538 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
626 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
701 void ARMBaseInstrInfo::
801 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
847 unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
853 void ARMBaseInstrInfo::
947 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
993 unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
999 bool ARMBaseInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const{
1066 ARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
1119 void ARMBaseInstrInfo::
1148 ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
1163 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
1253 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1328 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1349 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1389 bool ARMBaseInstrInfo::
1405 bool ARMBaseInstrInfo::
1513 const ARMBaseInstrInfo &TII, unsigned MIFlags) {
1539 const ARMBaseInstrInfo &TII) {
1678 bool ARMBaseInstrInfo::
1731 bool ARMBaseInstrInfo::
1878 bool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI,
1976 ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
2082 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
2123 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
2158 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
2198 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
2227 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2339 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2497 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2669 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
2691 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
2709 bool ARMBaseInstrInfo::
2729 bool ARMBaseInstrInfo::
2744 bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr *MI,
2754 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
2789 ARMBaseInstrInfo::getExecutionDomain(const MachineInstr *MI) const {
2813 ARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
