Lines Matching refs:NumVecs
208 /// SelectVLD - Select NEON load intrinsics. NumVecs should be
211 /// For NumVecs <= 2, QOpcodes1 is not used.
212 SDNode *SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
216 /// SelectVST - Select NEON store intrinsics. NumVecs should
219 /// For NumVecs <= 2, QOpcodes1 is not used.
220 SDNode *SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
224 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should
228 bool isUpdating, unsigned NumVecs,
231 /// SelectVLDDup - Select NEON load-duplicate intrinsics. NumVecs
234 SDNode *SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs,
237 /// SelectVTBL - Select NEON VTBL and VTBX intrinsics. NumVecs should be 2,
240 SDNode *SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc);
284 SDValue GetVLDSTAlign(SDValue Align, unsigned NumVecs, bool is64BitVector);
1533 SDValue ARMDAGToDAGISel::GetVLDSTAlign(SDValue Align, unsigned NumVecs,
1535 unsigned NumRegs = NumVecs;
1536 if (!is64BitVector && NumVecs < 3)
1552 SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
1555 assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range");
1566 Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1583 assert(NumVecs == 1 && "v2i64 type only supported for VLD1");
1588 if (NumVecs == 1)
1591 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1608 if (is64BitVector || NumVecs <= 2) {
1659 if (NumVecs == 1)
1667 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1670 ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1));
1672 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLd, 2));
1676 SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
1679 assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range");
1694 Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1711 assert(NumVecs == 1 && "v2i64 type only supported for VST1");
1725 if (is64BitVector || NumVecs <= 2) {
1727 if (NumVecs == 1) {
1733 if (NumVecs == 2)
1739 SDValue V3 = (NumVecs == 3)
1779 SDValue V3 = (NumVecs == 3)
1814 bool isUpdating, unsigned NumVecs,
1817 assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");
1831 cast<ConstantSDNode>(N->getOperand(Vec0Idx + NumVecs))->getZExtValue();
1836 if (NumVecs != 3) {
1838 unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
1866 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1890 if (NumVecs == 2) {
1897 SDValue V3 = (NumVecs == 3)
1924 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1927 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, 1));
1929 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdLn, 2));
1934 unsigned NumVecs, unsigned *Opcodes) {
1935 assert(NumVecs >=2 && NumVecs <= 4 && "VLDDup NumVecs out-of-range");
1949 if (NumVecs != 3) {
1951 unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
1987 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
2001 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
2004 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdDup, 1));
2006 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdDup, 2));
2010 SDNode *ARMDAGToDAGISel::SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs,
2012 assert(NumVecs >= 2 && NumVecs <= 4 && "VTBL NumVecs out-of-range");
2021 if (NumVecs == 2)
2027 SDValue V3 = (NumVecs == 3)
2037 Ops.push_back(N->getOperand(FirstTblReg + NumVecs));
