Lines Matching refs:ShiftTy
343 ARM_AM::ShiftOpc ShiftTy;
352 ARM_AM::ShiftOpc ShiftTy;
358 ARM_AM::ShiftOpc ShiftTy;
675 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift;
720 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
974 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
982 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
1409 PostIdxReg.ShiftTy);
1511 Op->RegShiftedReg.ShiftTy = ShTy;
1525 Op->RegShiftedImm.ShiftTy = ShTy;
1629 ARM_AM::ShiftOpc ShiftTy,
1635 Op->PostIdxReg.ShiftTy = ShiftTy;
1715 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
1716 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
1869 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
1877 if (ShiftTy == ARM_AM::no_shift)
1891 if (ShiftTy == ARM_AM::rrx) {
1917 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
1918 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
1936 if (ShiftReg && ShiftTy != ARM_AM::rrx)
1937 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
1941 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2715 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
2719 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
2723 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
