Lines Matching refs:SETCC
182 // X86 is weird, it always uses i8 for shift amounts and setcc results.
424 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
425 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
426 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
427 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
428 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
429 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
432 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
725 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand);
803 setOperationAction(ISD::SETCC, MVT::v4f32, Custom);
833 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
834 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
835 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
836 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
972 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
1024 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1025 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1026 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1027 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
8191 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
8196 if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC)
8235 User->getOpcode() != ISD::SETCC &&
8363 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8374 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
8400 // If the input is a setcc, then reuse the input setcc
8402 if (Op0.getOpcode() == X86ISD::SETCC) {
8409 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8420 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8429 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC &&
8634 if (Cond.getOpcode() == ISD::SETCC) {
8644 if (Cond.getOpcode() == X86ISD::SETCC &&
8682 // setting operand in place of the X86ISD::SETCC.
8683 if (Cond.getOpcode() == X86ISD::SETCC ||
8750 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
8756 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8758 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
8762 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
8763 // 1 and that the SETCC node has a single use.
8769 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8783 if (Cond.getOpcode() == ISD::SETCC) {
8806 // setting operand in place of the X86ISD::SETCC.
8807 if (Cond.getOpcode() == X86ISD::SETCC ||
8883 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
9231 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9233 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9250 // or testp pattern and a setcc for the result.
9310 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
9311 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
10044 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
10045 // looks for this combo and may remove the "setcc" instruction if the "setcc"
10096 SDValue SetCC =
10097 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10101 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10109 SDValue SetCC =
10110 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
10114 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10418 case ISD::SETCC: return LowerSETCC(Op, DAG);
10642 case X86ISD::SETCC: return "X86ISD::SETCC";
12329 case X86ISD::SETCC:
12646 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
12798 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
12820 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
12918 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
12922 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12936 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
12939 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12977 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13211 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
14041 // ISD::SETCC is always legalized to i8.
14063 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
14139 SDValue SetCC = Ext.getOperand(0);
14140 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
14143 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
14147 SDValue Cmp = SetCC.getOperand(1);
14223 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
