Lines Matching defs:StackSlot
97 // Map from StackSlot to the LiveInterval of the original register.
103 // Map from pair of (StackSlot and Original VNI) to a set of spills which
104 // have the same stackslot and have equal values defined by Original VNI.
148 void addToMergeableSpills(MachineInstr &Spill, int StackSlot,
150 bool rmFromMergeableSpills(MachineInstr &Spill, int StackSlot);
171 int StackSlot;
174 // All registers to spill to StackSlot, including the main register.
297 if (SnipLI.reg == TII.isLoadFromStackSlot(MI, FI) && FI == StackSlot)
301 if (SnipLI.reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot)
409 TII.storeRegToStackSlot(*MBB, MII, SrcReg, false, StackSlot,
415 HSpiller.addToMergeableSpills(*MII, StackSlot, Original);
468 if (Reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot) {
474 if (HSpiller.rmFromMergeableSpills(MI, StackSlot))
684 /// If MI is a load or store of StackSlot, it can be removed.
693 if (InstrReg != Reg || FI != StackSlot)
697 HSpiller.rmFromMergeableSpills(*MI, StackSlot);
806 : TII.foldMemoryOperand(*MI, FoldOps, StackSlot, &LIS);
863 HSpiller.addToMergeableSpills(*FoldMI, StackSlot, Original);
875 TII.loadRegFromStackSlot(MBB, MI, NewVReg, StackSlot,
915 TII.storeRegToStackSlot(MBB, std::next(MI), NewVReg, isKill, StackSlot,
924 HSpiller.addToMergeableSpills(*std::next(MI), StackSlot, Original);
943 buildDbgValueForSpill(*MBB, MI, *MI, StackSlot);
1031 if (StackSlot == VirtRegMap::NO_STACK_SLOT) {
1032 StackSlot = VRM.assignVirt2StackSlot(Original);
1033 StackInt = &LSS.getOrCreateInterval(StackSlot, MRI.getRegClass(Original));
1036 StackInt = &LSS.getInterval(StackSlot);
1039 VRM.assignVirt2StackSlot(Edit->getReg(), StackSlot);
1082 StackSlot = VRM.getStackSlot(Original);
1107 void HoistSpillHelper::addToMergeableSpills(MachineInstr &Spill, int StackSlot,
1113 if (StackSlotToOrigLI.find(StackSlot) == StackSlotToOrigLI.end()) {
1116 StackSlotToOrigLI[StackSlot] = std::move(LI);
1119 VNInfo *OrigVNI = StackSlotToOrigLI[StackSlot]->getVNInfoAt(Idx.getRegSlot());
1120 std::pair<int, VNInfo *> MIdx = std::make_pair(StackSlot, OrigVNI);
1127 int StackSlot) {
1128 auto It = StackSlotToOrigLI.find(StackSlot);
1133 std::pair<int, VNInfo *> MIdx = std::make_pair(StackSlot, OrigVNI);
1498 /// stackslot as the \p old register.
1505 llvm_unreachable("VReg should be assigned either physreg or stackslot");
