Lines Matching refs:SETCC
64 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
337 if (Cond->getOpcode() == ISD::SETCC) {
429 // Turn it into a scalar SETCC.
430 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
481 case ISD::SETCC:
561 /// result must be v1i1, so just convert to a scalar SETCC and wrap
576 // Turn it into a scalar SETCC.
577 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
671 case ISD::SETCC:
1598 case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break;
2213 LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2));
2214 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2));
2279 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break;
3077 // a SETCC or a previously handled SETCC by convertMask().
3098 return (N.getOpcode() == ISD::SETCC ||
3107 // Currently a SETCC or a AND/OR/XOR with two SETCCs are handled.
3159 EVT DAGTypeLegalizer::getSETCCWidenedResultTy(SDValue SetCC) {
3160 assert(SetCC->getOpcode() == ISD::SETCC);
3162 EVT MaskVT = getSetCCResultType(SetCC->getOperand(0).getValueType());
3171 // scalarization of the SETCC, with many unnecessary instructions.
3179 if (Cond->getOpcode() != ISD::SETCC && !isLogicalMaskOp(Cond->getOpcode()))
3202 if (Cond.getOpcode() == ISD::SETCC) {
3234 if (Cond->getOpcode() == ISD::SETCC) {
3238 Cond->getOperand(0).getOpcode() == ISD::SETCC &&
3239 Cond->getOperand(1).getOpcode() == ISD::SETCC) {
3240 // Cond is (AND/OR/XOR (SETCC, SETCC))
3385 return DAG.getNode(ISD::SETCC, SDLoc(N),
3418 case ISD::SETCC: Res = WidenVecOp_SETCC(N); break;
3728 // Get a new SETCC node to compare the newly widened operands.
3732 // The result type is legal, if its vXi1, keep vXi1 for the new SETCC.
3737 SDValue WideSETCC = DAG.getNode(ISD::SETCC, SDLoc(N),
