Lines Matching refs:ArchKind
74 ArchNames<ARM::ArchKind> ARCHNames[] = {
77 sizeof(SUB_ARCH) - 1, ARCH_FPU, ARCH_BASE_EXT, ARM::ArchKind::ID, ARCH_ATTR},
81 ArchNames<AArch64::ArchKind> AArch64ARCHNames[] = {
84 sizeof(SUB_ARCH) - 1, ARCH_FPU, ARCH_BASE_EXT, AArch64::ArchKind::ID, ARCH_ATTR},
137 CpuNames<ARM::ArchKind> CPUNames[] = {
139 { NAME, sizeof(NAME) - 1, ARM::ArchKind::ID, IS_DEFAULT, DEFAULT_EXT },
143 CpuNames<AArch64::ArchKind> AArch64CPUNames[] = {
145 { NAME, sizeof(NAME) - 1, AArch64::ArchKind::ID, IS_DEFAULT, DEFAULT_EXT },
179 unsigned llvm::ARM::getDefaultFPU(StringRef CPU, ArchKind AK) {
190 unsigned llvm::ARM::getDefaultExtensions(StringRef CPU, ArchKind AK) {
196 .Case(NAME, ARCHNames[static_cast<unsigned>(ARM::ArchKind::ID)]\
332 StringRef llvm::ARM::getArchName(ArchKind AK) {
336 StringRef llvm::ARM::getCPUAttr(ArchKind AK) {
340 StringRef llvm::ARM::getSubArch(ArchKind AK) {
344 unsigned llvm::ARM::getArchAttr(ArchKind AK) {
381 ArchKind AK = parseArch(Arch);
382 if (AK == ARM::ArchKind::INVALID)
411 unsigned llvm::AArch64::getDefaultFPU(StringRef CPU, ArchKind AK) {
422 unsigned llvm::AArch64::getDefaultExtensions(StringRef CPU, ArchKind AK) {
429 AArch64ARCHNames[static_cast<unsigned>(AArch64::ArchKind::ID)] \
436 AArch64::ArchKind llvm::AArch64::getCPUArchKind(StringRef CPU) {
438 return AArch64::ArchKind::ARMV8A;
440 return StringSwitch<AArch64::ArchKind>(CPU)
442 .Case(NAME, AArch64::ArchKind:: ID)
444 .Default(AArch64::ArchKind::INVALID);
486 bool llvm::AArch64::getArchFeatures(AArch64::ArchKind AK,
488 if (AK == AArch64::ArchKind::ARMV8_1A)
490 if (AK == AArch64::ArchKind::ARMV8_2A)
492 if (AK == AArch64::ArchKind::ARMV8_3A)
494 if (AK == AArch64::ArchKind::ARMV8_4A)
497 return AK != AArch64::ArchKind::INVALID;
500 StringRef llvm::AArch64::getArchName(ArchKind AK) {
504 StringRef llvm::AArch64::getCPUAttr(ArchKind AK) {
508 StringRef llvm::AArch64::getSubArch(ArchKind AK) {
512 unsigned llvm::AArch64::getArchAttr(ArchKind AK) {
539 AArch64::ArchKind AK = parseArch(Arch);
540 if (AK == ArchKind::INVALID)
680 ARM::ArchKind ARM::parseArch(StringRef Arch) {
687 return ARM::ArchKind::INVALID;
698 ARM::ArchKind llvm::ARM::parseCPUArch(StringRef CPU) {
703 return ARM::ArchKind::INVALID;
707 for (const CpuNames<ARM::ArchKind> &Arch : CPUNames) {
708 if (Arch.ArchID != ARM::ArchKind::INVALID)
714 for (const CpuNames<AArch64::ArchKind> &Arch : AArch64CPUNames) {
715 if (Arch.ArchID != AArch64::ArchKind::INVALID)
753 case ARM::ArchKind::ARMV6M:
754 case ARM::ArchKind::ARMV7M:
755 case ARM::ArchKind::ARMV7EM:
756 case ARM::ArchKind::ARMV8MMainline:
757 case ARM::ArchKind::ARMV8MBaseline:
759 case ARM::ArchKind::ARMV7R:
760 case ARM::ArchKind::ARMV8R:
762 case ARM::ArchKind::ARMV7A:
763 case ARM::ArchKind::ARMV7VE:
764 case ARM::ArchKind::ARMV7K:
765 case ARM::ArchKind::ARMV8A:
766 case ARM::ArchKind::ARMV8_1A:
767 case ARM::ArchKind::ARMV8_2A:
768 case ARM::ArchKind::ARMV8_3A:
769 case ARM::ArchKind::ARMV8_4A:
771 case ARM::ArchKind::ARMV2:
772 case ARM::ArchKind::ARMV2A:
773 case ARM::ArchKind::ARMV3:
774 case ARM::ArchKind::ARMV3M:
775 case ARM::ArchKind::ARMV4:
776 case ARM::ArchKind::ARMV4T:
777 case ARM::ArchKind::ARMV5T:
778 case ARM::ArchKind::ARMV5TE:
779 case ARM::ArchKind::ARMV5TEJ:
780 case ARM::ArchKind::ARMV6:
781 case ARM::ArchKind::ARMV6K:
782 case ARM::ArchKind::ARMV6T2:
783 case ARM::ArchKind::ARMV6KZ:
784 case ARM::ArchKind::ARMV7S:
785 case ARM::ArchKind::IWMMXT:
786 case ARM::ArchKind::IWMMXT2:
787 case ARM::ArchKind::XSCALE:
788 case ARM::ArchKind::INVALID:
798 case ARM::ArchKind::ARMV2:
799 case ARM::ArchKind::ARMV2A:
801 case ARM::ArchKind::ARMV3:
802 case ARM::ArchKind::ARMV3M:
804 case ARM::ArchKind::ARMV4:
805 case ARM::ArchKind::ARMV4T:
807 case ARM::ArchKind::ARMV5T:
808 case ARM::ArchKind::ARMV5TE:
809 case ARM::ArchKind::IWMMXT:
810 case ARM::ArchKind::IWMMXT2:
811 case ARM::ArchKind::XSCALE:
812 case ARM::ArchKind::ARMV5TEJ:
814 case ARM::ArchKind::ARMV6:
815 case ARM::ArchKind::ARMV6K:
816 case ARM::ArchKind::ARMV6T2:
817 case ARM::ArchKind::ARMV6KZ:
818 case ARM::ArchKind::ARMV6M:
820 case ARM::ArchKind::ARMV7A:
821 case ARM::ArchKind::ARMV7VE:
822 case ARM::ArchKind::ARMV7R:
823 case ARM::ArchKind::ARMV7M:
824 case ARM::ArchKind::ARMV7S:
825 case ARM::ArchKind::ARMV7EM:
826 case ARM::ArchKind::ARMV7K:
828 case ARM::ArchKind::ARMV8A:
829 case ARM::ArchKind::ARMV8_1A:
830 case ARM::ArchKind::ARMV8_2A:
831 case ARM::ArchKind::ARMV8_3A:
832 case ARM::ArchKind::ARMV8_4A:
833 case ARM::ArchKind::ARMV8R:
834 case ARM::ArchKind::ARMV8MBaseline:
835 case ARM::ArchKind::ARMV8MMainline:
837 case ARM::ArchKind::INVALID:
888 AArch64::ArchKind AArch64::parseArch(StringRef Arch) {
891 return ArchKind::INVALID;
898 return ArchKind::INVALID;
909 AArch64::ArchKind llvm::AArch64::parseCPUArch(StringRef CPU) {
914 return ArchKind::INVALID;
