Lines Matching refs:NumVecs
151 void SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, bool isExt);
155 void SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
157 void SelectPostLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
159 void SelectLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
160 void SelectPostLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
162 void SelectStore(SDNode *N, unsigned NumVecs, unsigned Opc);
163 void SelectPostStore(SDNode *N, unsigned NumVecs, unsigned Opc);
164 void SelectStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
165 void SelectPostStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
1076 void AArch64DAGToDAGISel::SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc,
1086 N->op_begin() + Vec0Off + NumVecs);
1093 Ops.push_back(N->getOperand(NumVecs + ExtOff + 1));
1191 void AArch64DAGToDAGISel::SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
1204 for (unsigned i = 0; i < NumVecs; ++i)
1208 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1));
1218 void AArch64DAGToDAGISel::SelectPostLoad(SDNode *N, unsigned NumVecs,
1234 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 0));
1238 if (NumVecs == 1)
1241 for (unsigned i = 0; i < NumVecs; ++i)
1246 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(Ld, 2));
1250 void AArch64DAGToDAGISel::SelectStore(SDNode *N, unsigned NumVecs,
1257 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);
1260 SDValue Ops[] = {RegSeq, N->getOperand(NumVecs + 2), N->getOperand(0)};
1271 void AArch64DAGToDAGISel::SelectPostStore(SDNode *N, unsigned NumVecs,
1280 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);
1284 N->getOperand(NumVecs + 1), // base register
1285 N->getOperand(NumVecs + 2), // Incremental
1327 void AArch64DAGToDAGISel::SelectLoadLane(SDNode *N, unsigned NumVecs,
1334 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);
1345 cast<ConstantSDNode>(N->getOperand(NumVecs + 2))->getZExtValue();
1348 N->getOperand(NumVecs + 3), N->getOperand(0)};
1355 for (unsigned i = 0; i < NumVecs; ++i) {
1362 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1));
1366 void AArch64DAGToDAGISel::SelectPostLoadLane(SDNode *N, unsigned NumVecs,
1373 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);
1385 cast<ConstantSDNode>(N->getOperand(NumVecs + 1))->getZExtValue();
1390 N->getOperand(NumVecs + 2), // Base register
1391 N->getOperand(NumVecs + 3), // Incremental
1396 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 0));
1400 if (NumVecs == 1) {
1407 for (unsigned i = 0; i < NumVecs; ++i) {
1417 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(Ld, 2));
1421 void AArch64DAGToDAGISel::SelectStoreLane(SDNode *N, unsigned NumVecs,
1428 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);
1437 cast<ConstantSDNode>(N->getOperand(NumVecs + 2))->getZExtValue();
1440 N->getOperand(NumVecs + 3), N->getOperand(0)};
1451 void AArch64DAGToDAGISel::SelectPostStoreLane(SDNode *N, unsigned NumVecs,
1458 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);
1470 cast<ConstantSDNode>(N->getOperand(NumVecs + 1))->getZExtValue();
1473 N->getOperand(NumVecs + 2), // Base Register
1474 N->getOperand(NumVecs + 3), // Incremental
