Lines Matching refs:CSel
994 case AArch64ISD::CSEL: {
1093 case AArch64ISD::CSEL: return "AArch64ISD::CSEL";
2048 // (csel 1, 0, invert(cc), overflow_op_bool)
2062 return DAG.getNode(AArch64ISD::CSEL, dl, Op.getValueType(), TVal, FVal,
2074 // (csel x, (xor x, -1), cc ...)
2112 return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal,
2174 Overflow = DAG.getNode(AArch64ISD::CSEL, dl, MVT::i32, FVal, TVal,
4531 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp);
4538 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
4551 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp);
4555 // this case, we emit the first CSEL and then emit a second using the output
4561 DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
4564 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
4596 unsigned Opcode = AArch64ISD::CSEL;
4613 // with a CSINV rather than a CSEL.
4621 // that we can match with a CSNEG rather than a CSEL.
4634 // instead of a CSEL in that case.
4671 if (Opcode != AArch64ISD::CSEL) {
4680 // is one, zero or negative one in the case of a CSEL. We can always
4681 // materialize these values using CSINC, CSEL and CSINV with wzr/xzr as the
4684 if (Opcode == AArch64ISD::CSEL && RHSVal && !RHSVal->isOne() &&
4741 // Emit first, and possibly only, CSEL.
4743 SDValue CS1 = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
4745 // If we need a second CSEL, emit it, using the output of the first as the
4749 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
4752 // Otherwise, return the output of the first CSEL.
4786 return DAG.getNode(AArch64ISD::CSEL, DL, Op.getValueType(), TVal, FVal,
5111 // is "undef". We wanted 0, so CSEL it directly.
5116 DAG.getNode(AArch64ISD::CSEL, dl, VT, DAG.getConstant(0, dl, MVT::i64),
5130 SDValue Lo = DAG.getNode(AArch64ISD::CSEL, dl, VT, LoForBigShift,
5141 SDValue Hi = DAG.getNode(AArch64ISD::CSEL, dl, VT, HiForBigShift,
5166 // is "undef". We wanted 0, so CSEL it directly.
5171 DAG.getNode(AArch64ISD::CSEL, dl, VT, DAG.getConstant(0, dl, MVT::i64),
5185 SDValue Hi = DAG.getNode(AArch64ISD::CSEL, dl, VT, HiForBigShift,
5192 SDValue Lo = DAG.getNode(AArch64ISD::CSEL, dl, VT, LoForBigShift,
8572 // Generate SUBS and CSEL for integer abs.
8581 // and change it to SUB and CSEL.
8589 // Generate SUBS & CSEL.
8593 return DAG.getNode(AArch64ISD::CSEL, DL, VT, N0.getOperand(0), Neg,
8636 SDValue CSel = DAG.getNode(AArch64ISD::CSEL, DL, VT, Add, N0, CCVal, Cmp);
8640 Created.push_back(CSel.getNode());
8644 DAG.getNode(ISD::SRA, DL, VT, CSel, DAG.getConstant(Lg2, DL, MVT::i64));
9435 // Otherwise, check if this is a matching csel instruction.
9437 // - csel 1, 0, cc
9438 // - csel 0, 1, !cc
9439 if (Op.getOpcode() != AArch64ISD::CSEL)
9442 // TODO: we want the operands of the Cmp not the csel
9479 // (csel x, (add x, 1), !cc ...)
9518 return DAG.getNode(AArch64ISD::CSEL, dl, VT, RHS, LHS, CCVal, Cmp);
10966 case AArch64ISD::CSEL:
