Lines Matching refs:f128
137 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);
208 // Virtually no operation on f128 is legal, but LLVM can't expand them when
210 setOperationAction(ISD::FABS, MVT::f128, Expand);
211 setOperationAction(ISD::FADD, MVT::f128, Custom);
212 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
213 setOperationAction(ISD::FCOS, MVT::f128, Expand);
214 setOperationAction(ISD::FDIV, MVT::f128, Custom);
215 setOperationAction(ISD::FMA, MVT::f128, Expand);
216 setOperationAction(ISD::FMUL, MVT::f128, Custom);
217 setOperationAction(ISD::FNEG, MVT::f128, Expand);
218 setOperationAction(ISD::FPOW, MVT::f128, Expand);
219 setOperationAction(ISD::FREM, MVT::f128, Expand);
220 setOperationAction(ISD::FRINT, MVT::f128, Expand);
221 setOperationAction(ISD::FSIN, MVT::f128, Expand);
222 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
223 setOperationAction(ISD::FSQRT, MVT::f128, Expand);
224 setOperationAction(ISD::FSUB, MVT::f128, Custom);
225 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
226 setOperationAction(ISD::SETCC, MVT::f128, Custom);
227 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
228 setOperationAction(ISD::SELECT, MVT::f128, Custom);
229 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
230 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
232 // Lowering for many of the conversions is actually specified by the non-f128
233 // type. The LowerXXX function will be trivial when f128 isn't involved.
516 setTruncStoreAction(MVT::f128, MVT::f80, Expand);
517 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
518 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
519 setTruncStoreAction(MVT::f128, MVT::f16, Expand);
1469 assert(VT != MVT::f128);
1575 assert(LHS.getValueType() != MVT::f128);
1620 if (Val->getOperand(0).getValueType() == MVT::f128)
2027 return makeLibCall(DAG, Call, MVT::f128, Ops, false, SDLoc(Op)).first;
2214 assert(Op.getValueType() == MVT::f128 && "Unexpected lowering");
2224 if (Op.getOperand(0).getValueType() != MVT::f128) {
2225 // It's legal except when f128 is involved
2292 if (Op.getOperand(0).getValueType() != MVT::f128) {
2293 // It's legal except when f128 is involved
2356 if (Op.getValueType() != MVT::f128)
3022 else if (RegVT == MVT::f128 || RegVT.is128BitVector())
3206 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f128);
4267 // Handle f128 first, since lowering it will result in comparing the return
4270 if (LHS.getValueType() == MVT::f128) {
4271 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
4510 // Handle f128 first, since one possible outcome is a normal integer
4512 if (LHS.getValueType() == MVT::f128) {
4513 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
4572 // Handle f128 first, because it will result in a comparison of some RTLIB
4574 if (LHS.getValueType() == MVT::f128) {
4575 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
5208 // FIXME: We should be able to handle f128 as well with a clever lowering.
8359 (allowsMisalignedMemoryAccesses(MVT::f128, 0, 1, &Fast) && Fast)))
8360 return MVT::f128;
