Lines Matching defs:AMDGPUTargetLowering
121 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {
130 unsigned AMDGPUTargetLowering::numBitsUnsigned(SDValue Op, SelectionDAG &DAG) {
138 unsigned AMDGPUTargetLowering::numBitsSigned(SDValue Op, SelectionDAG &DAG) {
146 AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
606 bool AMDGPUTargetLowering::allUsesHaveSourceMods(const SDNode *N,
630 MVT AMDGPUTargetLowering::getVectorIdxTy(const DataLayout &) const {
634 bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const {
640 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
647 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {
652 bool AMDGPUTargetLowering::shouldReduceLoadWidth(SDNode *N,
675 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy,
694 bool AMDGPUTargetLowering::isCheapToSpeculateCttz() const {
698 bool AMDGPUTargetLowering::isCheapToSpeculateCtlz() const {
702 bool AMDGPUTargetLowering::isSDNodeAlwaysUniform(const SDNode * N) const {
737 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
745 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
752 bool AMDGPUTargetLowering:: storeOfVectorConstantIsCheap(EVT MemVT,
758 bool AMDGPUTargetLowering::aggressivelyPreferBuildVectorSources(EVT VecVT) const {
770 bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {
779 bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {
791 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
801 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
813 bool AMDGPUTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
817 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
903 void AMDGPUTargetLowering::analyzeFormalArgumentsCompute(
1013 SDValue AMDGPUTargetLowering::LowerReturn(
1030 CCAssignFn *AMDGPUTargetLowering::CCAssignFnForCall(CallingConv::ID CC,
1035 CCAssignFn *AMDGPUTargetLowering::CCAssignFnForReturn(CallingConv::ID CC,
1040 SDValue AMDGPUTargetLowering::addTokenForArgument(SDValue Chain,
1076 SDValue AMDGPUTargetLowering::lowerUnhandledCall(CallLoweringInfo &CLI,
1103 SDValue AMDGPUTargetLowering::LowerCall(CallLoweringInfo &CLI,
1108 SDValue AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
1119 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
1158 void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
1183 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
1218 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
1238 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
1251 SDValue AMDGPUTargetLowering::combineFMinMaxLegacy(const SDLoc &DL, EVT VT,
1325 AMDGPUTargetLowering::split64BitValue(SDValue Op, SelectionDAG &DAG) const {
1339 SDValue AMDGPUTargetLowering::getLoHalf64(SDValue Op, SelectionDAG &DAG) const {
1347 SDValue AMDGPUTargetLowering::getHiHalf64(SDValue Op, SelectionDAG &DAG) const {
1355 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue Op,
1402 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
1446 SDValue AMDGPUTargetLowering::LowerDIVREM24(SDValue Op, SelectionDAG &DAG,
1552 void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op,
1762 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
1877 SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,
1938 SDValue AMDGPUTargetLowering::LowerFREM(SDValue Op, SelectionDAG &DAG) const {
1953 SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const {
1993 SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {
2042 SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {
2069 SDValue AMDGPUTargetLowering::LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const {
2081 SDValue AMDGPUTargetLowering::LowerFROUND32_16(SDValue Op, SelectionDAG &DAG) const {
2110 SDValue AMDGPUTargetLowering::LowerFROUND64(SDValue Op, SelectionDAG &DAG) const {
2167 SDValue AMDGPUTargetLowering::LowerFROUND(SDValue Op, SelectionDAG &DAG) const {
2179 SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {
2204 SDValue AMDGPUTargetLowering::LowerFLOG(SDValue Op, SelectionDAG &DAG,
2224 SDValue AMDGPUTargetLowering::LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const {
2298 SDValue AMDGPUTargetLowering::LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG,
2383 SDValue AMDGPUTargetLowering::LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG,
2406 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
2433 SDValue AMDGPUTargetLowering::LowerSINT_TO_FP(SDValue Op,
2460 SDValue AMDGPUTargetLowering::LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG,
2489 SDValue AMDGPUTargetLowering::LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const {
2588 SDValue AMDGPUTargetLowering::LowerFP_TO_SINT(SDValue Op,
2611 SDValue AMDGPUTargetLowering::LowerFP_TO_UINT(SDValue Op,
2634 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
2662 return AMDGPUTargetLowering::numBitsUnsigned(Op, DAG) <= 24;
2669 AMDGPUTargetLowering::numBitsSigned(Op, DAG) < 24;
2712 bool AMDGPUTargetLowering::shouldCombineMemoryType(EVT VT) const {
2733 SDValue AMDGPUTargetLowering::performLoadCombine(SDNode *N,
2784 SDValue AMDGPUTargetLowering::performStoreCombine(SDNode *N,
2840 SDValue AMDGPUTargetLowering::performAssertSZExtCombine(SDNode *N,
2864 SDValue AMDGPUTargetLowering::splitBinaryBitConstantOpImpl(
2887 SDValue AMDGPUTargetLowering::performShlCombine(SDNode *N,
2956 SDValue AMDGPUTargetLowering::performSraCombine(SDNode *N,
2991 SDValue AMDGPUTargetLowering::performSrlCombine(SDNode *N,
3026 SDValue AMDGPUTargetLowering::performTruncateCombine(
3136 SDValue AMDGPUTargetLowering::performMulCombine(SDNode *N,
3183 SDValue AMDGPUTargetLowering::performMulhsCombine(SDNode *N,
3207 SDValue AMDGPUTargetLowering::performMulhuCombine(SDNode *N,
3231 SDValue AMDGPUTargetLowering::performMulLoHi24Combine(
3260 SDValue AMDGPUTargetLowering::getFFBX_U32(SelectionDAG &DAG,
3287 SDValue AMDGPUTargetLowering::performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond,
3404 SDValue AMDGPUTargetLowering::performSelectCombine(SDNode *N,
3473 SDValue AMDGPUTargetLowering::performFNegCombine(SDNode *N,
3654 SDValue AMDGPUTargetLowering::performFAbsCombine(SDNode *N,
3679 SDValue AMDGPUTargetLowering::performRcpCombine(SDNode *N,
3691 SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
3905 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
3927 SDValue AMDGPUTargetLowering::loadStackInputValue(SelectionDAG &DAG,
3943 SDValue AMDGPUTargetLowering::storeStackInputValue(SelectionDAG &DAG,
3958 SDValue AMDGPUTargetLowering::loadInputValue(SelectionDAG &DAG,
3969 uint32_t AMDGPUTargetLowering::getImplicitParameterOffset(
3989 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
4134 SDValue AMDGPUTargetLowering::getSqrtEstimate(SDValue Operand,
4152 SDValue AMDGPUTargetLowering::getRecipEstimate(SDValue Operand,
4173 void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
4290 unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(
