Lines Matching refs:FMA
473 setOperationAction(ISD::FMA, MVT::f16, Legal);
568 setOperationAction(ISD::FMA, MVT::v2f16, Legal);
626 setTargetDAGCombine(ISD::FMA);
686 (Opcode == ISD::FMA && Subtarget->hasFmaMixInsts())) &&
3477 // This currently forces unfolding various combinations of fsub into fma with
3478 // free fneg'd operands. As long as we have fast FMA (controlled by
3481 // When fma is quarter rate, for f64 where add / sub are at best half rate,
3502 // have different rates for fma or all f64 operations.
3513 // however does not support denormals, so we do report fma as faster if we have
3514 // a fast fma device and require denormals.
3523 // which we should prefer over fma. We can't use this if we want to support
5808 case ISD::FMA:
5916 SDValue Fma0 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, NegDivScale0,
5919 SDValue Fma1 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, Fma0, ApproxRcp,
5925 SDValue Fma2 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, NegDivScale0, Mul,
5928 SDValue Fma3 = getFPTernOp(DAG, ISD::FMA,SL, MVT::f32, Fma2, Fma1, Mul, Fma2);
5930 SDValue Fma4 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, NegDivScale0, Fma3,
5972 SDValue Fma0 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Rcp, One);
5974 SDValue Fma1 = DAG.getNode(ISD::FMA, SL, MVT::f64, Rcp, Fma0, Rcp);
5976 SDValue Fma2 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Fma1, One);
5980 SDValue Fma3 = DAG.getNode(ISD::FMA, SL, MVT::f64, Fma1, Fma2, Fma1);
5983 SDValue Fma4 = DAG.getNode(ISD::FMA, SL, MVT::f64,
6693 case ISD::FMA:
6823 case ISD::FMA:
7334 return ISD::FMA;
7573 // FMA((F32)S0.x, (F32)S1. x, FMA((F32)S0.y, (F32)S1.y, (F32)z)) ->
7577 SDValue FMA = N->getOperand(2);
7579 if (FMA.getOpcode() != ISD::FMA ||
7590 FMA->getFlags().hasAllowContract())) {
7601 SDValue FMAOp1 = FMA.getOperand(0);
7602 SDValue FMAOp2 = FMA.getOperand(1);
7603 SDValue FMAAcc = FMA.getOperand(2);
7823 case ISD::FMA:
