Lines Matching refs:PhiReg
2820 unsigned PhiReg,
2832 BuildMI(LoopBB, I, DL, TII->get(TargetOpcode::PHI), PhiReg)
2913 unsigned PhiReg,
2954 InitResultReg, DstReg, PhiReg, TmpExec,
3085 unsigned PhiReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
3090 auto InsPt = loadM0FromVGPR(TII, MBB, MI, InitReg, PhiReg,
3200 unsigned PhiReg = MRI.createVirtualRegister(VecRC);
3202 auto InsPt = loadM0FromVGPR(TII, MBB, MI, SrcVec->getReg(), PhiReg,
3208 .addReg(PhiReg, RegState::Undef, SubReg) // vdst
3211 .addReg(PhiReg, RegState::Implicit)
3219 .addReg(PhiReg)
