Lines Matching refs:SITargetLowering
114 SITargetLowering::SITargetLowering(const TargetMachine &TM,
671 const GCNSubtarget *SITargetLowering::getSubtarget() const {
683 bool SITargetLowering::isFPExtFoldable(unsigned Opcode,
691 bool SITargetLowering::isShuffleMaskLegal(ArrayRef<int>, EVT) const {
697 MVT SITargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
719 unsigned SITargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,
741 unsigned SITargetLowering::getVectorTypeBreakdownForCallingConv(
778 bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
849 bool SITargetLowering::getAddrModeArguments(IntrinsicInst *II,
868 bool SITargetLowering::isLegalFlatAddressingMode(const AddrMode &AM) const {
882 bool SITargetLowering::isLegalGlobalAddressingMode(const AddrMode &AM) const {
902 bool SITargetLowering::isLegalMUBUFAddressingMode(const AddrMode &AM) const {
937 bool SITargetLowering::isLegalAddressingMode(const DataLayout &DL,
1017 bool SITargetLowering::canMergeStoresTo(unsigned AS, EVT MemVT,
1030 bool SITargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1092 EVT SITargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
1119 bool SITargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1125 bool SITargetLowering::isMemOpHasNoClobberedMemOperand(const SDNode *N) const {
1132 bool SITargetLowering::isCheapAddrSpaceCast(unsigned SrcAS,
1142 bool SITargetLowering::isMemOpUniform(const SDNode *N) const {
1149 SITargetLowering::getPreferredVectorAction(EVT VT) const {
1156 bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
1162 bool SITargetLowering::isTypeDesirableForOp(unsigned Op, EVT VT) const {
1188 SDValue SITargetLowering::lowerKernArgParameterPtr(SelectionDAG &DAG,
1210 SDValue SITargetLowering::getImplicitArgPtr(SelectionDAG &DAG,
1217 SDValue SITargetLowering::convertArgType(SelectionDAG &DAG, EVT VT, EVT MemVT,
1237 SDValue SITargetLowering::lowerKernargMemParameter(
1283 SDValue SITargetLowering::lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA,
1332 SDValue SITargetLowering::getPreloadedValue(SelectionDAG &DAG,
1706 bool SITargetLowering::supportSplitCSR(MachineFunction *MF) const {
1711 void SITargetLowering::initializeSplitCSR(MachineBasicBlock *Entry) const {
1715 void SITargetLowering::insertCopiesSplitCSR(
1750 SDValue SITargetLowering::LowerFormalArguments(
2008 bool SITargetLowering::CanLowerReturn(
2025 SITargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2168 SDValue SITargetLowering::LowerCallResult(
2226 void SITargetLowering::passSpecialInputs(
2322 bool SITargetLowering::isEligibleForTailCallOptimization(
2393 bool SITargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
2406 SDValue SITargetLowering::LowerCall(CallLoweringInfo &CLI,
2731 unsigned SITargetLowering::getRegisterByName(const char* RegName, EVT VT,
2779 MachineBasicBlock *SITargetLowering::splitKillBlock(MachineInstr &MI,
3229 MachineBasicBlock *SITargetLowering::EmitInstrWithCustomInserter(
3472 bool SITargetLowering::hasBitPreservingFPLogic(EVT VT) const {
3476 bool SITargetLowering::enableAggressiveFMAFusion(EVT VT) const {
3487 EVT SITargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &Ctx,
3495 MVT SITargetLowering::getScalarShiftAmountTy(const DataLayout &, EVT VT) const {
3516 bool SITargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
3548 SDValue SITargetLowering::splitUnaryVectorOp(SDValue Op,
3568 SDValue SITargetLowering::splitBinaryVectorOp(SDValue Op,
3589 SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
3678 SDValue SITargetLowering::adjustLoadValueType(unsigned Opcode,
3720 void SITargetLowering::ReplaceNodeResults(SDNode *N,
3849 unsigned SITargetLowering::isCFIntrinsic(const SDNode *Intr) const {
3870 void SITargetLowering::createDebuggerPrologueStackObjects(
3896 bool SITargetLowering::shouldEmitFixup(const GlobalValue *GV) const {
3903 bool SITargetLowering::shouldEmitGOTReloc(const GlobalValue *GV) const {
3911 bool SITargetLowering::shouldEmitPCReloc(const GlobalValue *GV) const {
3917 SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND,
4016 SDValue SITargetLowering::getFPExtOrFPTrunc(SelectionDAG &DAG,
4025 SDValue SITargetLowering::lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const {
4041 SDValue SITargetLowering::lowerTRAP(SDValue Op, SelectionDAG &DAG) const {
4067 SDValue SITargetLowering::lowerDEBUGTRAP(SDValue Op, SelectionDAG &DAG) const {
4090 SDValue SITargetLowering::getSegmentAperture(unsigned AS, const SDLoc &DL,
4139 SDValue SITargetLowering::lowerADDRSPACECAST(SDValue Op,
4198 SDValue SITargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op,
4274 SDValue SITargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op,
4315 SDValue SITargetLowering::lowerBUILD_VECTOR(SDValue Op,
4357 SITargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
4407 SDValue SITargetLowering::LowerGlobalAddress(AMDGPUMachineFunction *MFI,
4445 SDValue SITargetLowering::copyToM0(SelectionDAG &DAG, SDValue Chain,
4461 SDValue SITargetLowering::lowerImplicitZextParam(SelectionDAG &DAG,
4550 SDValue SITargetLowering::lowerImage(SDValue Op,
4745 SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
5086 SDValue SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
5264 SDValue SITargetLowering::handleD16VData(SDValue VData,
5290 SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,
5508 SDValue SITargetLowering::widenLoad(LoadSDNode *Ld, DAGCombinerInfo &DCI) const {
5578 SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
5695 SDValue SITargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
5724 SDValue SITargetLowering::lowerFastUnsafeFDIV(SDValue Op,
5817 SDValue SITargetLowering::LowerFDIV16(SDValue Op, SelectionDAG &DAG) const {
5838 SDValue SITargetLowering::lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const {
5871 SDValue SITargetLowering::LowerFDIV32(SDValue Op, SelectionDAG &DAG) const {
5954 SDValue SITargetLowering::LowerFDIV64(SDValue Op, SelectionDAG &DAG) const {
6021 SDValue SITargetLowering::LowerFDIV(SDValue Op, SelectionDAG &DAG) const {
6036 SDValue SITargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
6099 SDValue SITargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
6119 SDValue SITargetLowering::LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
6150 SDValue SITargetLowering::performUCharToFloatCombine(SDNode *N,
6192 SDValue SITargetLowering::performSHLPtrCombine(SDNode *N,
6239 SDValue SITargetLowering::performMemSDNodeCombine(MemSDNode *N,
6271 SDValue SITargetLowering::splitBinaryBitConstantOp(
6375 SDValue SITargetLowering::performAndCombine(SDNode *N,
6538 SDValue SITargetLowering::performOrCombine(SDNode *N,
6664 SDValue SITargetLowering::performXorCombine(SDNode *N,
6740 SDValue SITargetLowering::performZeroExtendCombine(SDNode *N,
6766 SDValue SITargetLowering::performClassCombine(SDNode *N,
6783 SDValue SITargetLowering::performRcpCombine(SDNode *N,
6874 SDValue SITargetLowering::performFCanonicalizeCombine(
6962 SDValue SITargetLowering::performIntMed3ImmCombine(
7012 SDValue SITargetLowering::performFPMed3ImmCombine(SelectionDAG &DAG,
7056 SDValue SITargetLowering::performMinMaxCombine(SDNode *N,
7137 SDValue SITargetLowering::performFMed3Combine(SDNode *N,
7178 SDValue SITargetLowering::performCvtPkRTZCombine(SDNode *N,
7187 SDValue SITargetLowering::performExtractVectorEltCombine(
7289 SDValue SITargetLowering::performBuildVectorCombine(
7318 unsigned SITargetLowering::getFusedOpcode(const SelectionDAG &DAG,
7350 SDValue SITargetLowering::performAddCombine(SDNode *N,
7423 SDValue SITargetLowering::performSubCombine(SDNode *N,
7450 SDValue SITargetLowering::performAddCarrySubCarryCombine(SDNode *N,
7475 SDValue SITargetLowering::performFAddCombine(SDNode *N,
7517 SDValue SITargetLowering::performFSubCombine(SDNode *N,
7564 SDValue SITargetLowering::performFMACombine(SDNode *N,
7639 SDValue SITargetLowering::performSetCCCombine(SDNode *N,
7725 SDValue SITargetLowering::performCvtF32UByteNCombine(SDNode *N,
7769 SDValue SITargetLowering::performClampCombine(SDNode *N,
7792 SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
7932 SDNode *SITargetLowering::adjustWritemask(MachineSDNode *&Node,
8061 SDNode *SITargetLowering::legalizeTargetIndependentNode(SDNode *Node,
8107 SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
8181 void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
8235 MachineSDNode *SITargetLowering::wrapAddr64Rsrc(SelectionDAG &DAG,
8270 MachineSDNode *SITargetLowering::buildRSRC(SelectionDAG &DAG, const SDLoc &DL,
8305 SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
8386 SITargetLowering::ConstraintType
8387 SITargetLowering::getConstraintType(StringRef Constraint) const {
8402 void SITargetLowering::finalizeLowering(MachineFunction &MF) const {
8441 void SITargetLowering::computeKnownBitsForFrameIndex(const SDValue Op,
8459 bool SITargetLowering::isSDNodeSourceOfDivergence(const SDNode * N,
