Lines Matching refs:SrcVec
3138 const MachineOperand *SrcVec = TII->getNamedOperand(MI, AMDGPU::OpName::src);
3142 const TargetRegisterClass *VecRC = MRI.getRegClass(SrcVec->getReg());
3149 SrcVec->getReg(),
3160 .add(*SrcVec)
3174 .addReg(SrcVec->getReg(), RegState::Undef, SubReg) // vdst
3177 .addReg(SrcVec->getReg(), RegState::Implicit)
3186 .addReg(SrcVec->getReg())
3202 auto InsPt = loadM0FromVGPR(TII, MBB, MI, SrcVec->getReg(), PhiReg,
