Cross Reference: /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

Lines Matching defs:AddDReg
958 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
1025           AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
1026           AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
1036           AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
1037           AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
1077           MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
1078           MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
1079           AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
1100           MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
1101           MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
1102           MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
1103                 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
1114         MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
1115         MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
1116         MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
1117         MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
1118         MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
1119         MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
1120         MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
1121               AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
1232         AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1233         AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1243         MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1244         MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1282         MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1283         MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1284         MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1304         MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1305         MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1306         MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1307         MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1320       MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1321       MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1322       MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1323       MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1324       MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI);
1325       MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI);
1326       MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI);
1327       MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI);
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