Lines Matching refs:CurReg
2319 unsigned CurReg = RegClass->getRegister(CurRegEnc);
2324 RegList.push_back(MachineOperand::CreateReg(CurReg, false, false,
2334 if (isCalleeSavedRegister(CurReg, CSRegs) ||
2335 MI->getParent()->computeRegisterLiveness(TRI, CurReg, MI) !=
2346 RegList.push_back(MachineOperand::CreateReg(CurReg, true, false, false,
4820 unsigned CurReg = SrcLane == 1 && DstLane == 1 ? DSrc : DDst;
4821 bool CurUndef = !MI.readsRegister(CurReg, TRI);
4822 NewMIB.addReg(CurReg, getUndefRegState(CurUndef));
4824 CurReg = SrcLane == 0 && DstLane == 0 ? DSrc : DDst;
4825 CurUndef = !MI.readsRegister(CurReg, TRI);
4826 NewMIB.addReg(CurReg, getUndefRegState(CurUndef))
4838 CurReg = SrcLane == 1 && DstLane == 0 ? DSrc : DDst;
4839 CurUndef = CurReg == DSrc && !MI.readsRegister(CurReg, TRI);
4840 MIB.addReg(CurReg, getUndefRegState(CurUndef));
4842 CurReg = SrcLane == 0 && DstLane == 1 ? DSrc : DDst;
4843 CurUndef = CurReg == DSrc && !MI.readsRegister(CurReg, TRI);
4844 MIB.addReg(CurReg, getUndefRegState(CurUndef))
