Lines Matching refs:NextReg
1227 unsigned NextReg = ARM::D8;
1232 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1238 .addReg(NextReg)
1241 NextReg += 4;
1247 unsigned R4BaseReg = NextReg;
1251 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1257 .addReg(NextReg)
1260 NextReg += 4;
1266 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1274 NextReg += 2;
1280 MBB.addLiveIn(NextReg);
1283 .addReg(NextReg)
1285 .addImm((NextReg - R4BaseReg) * 2)
1360 unsigned NextReg = ARM::D8;
1364 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1366 BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Qwb_fixed), NextReg)
1372 NextReg += 4;
1378 unsigned R4BaseReg = NextReg;
1382 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1384 BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Q), NextReg)
1389 NextReg += 4;
1395 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1401 NextReg += 2;
1407 BuildMI(MBB, MI, DL, TII.get(ARM::VLDRD), NextReg)
1409 .addImm(2 * (NextReg - R4BaseReg))
