Lines Matching refs:NumVecs
181 /// SelectVLD - Select NEON load intrinsics. NumVecs should be
184 /// For NumVecs <= 2, QOpcodes1 is not used.
185 void SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
189 /// SelectVST - Select NEON store intrinsics. NumVecs should
192 /// For NumVecs <= 2, QOpcodes1 is not used.
193 void SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
197 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should
201 unsigned NumVecs, const uint16_t *DOpcodes,
204 /// SelectVLDDup - Select NEON load-duplicate intrinsics. NumVecs
208 unsigned NumVecs, const uint16_t *DOpcodes,
244 SDValue GetVLDSTAlign(SDValue Align, const SDLoc &dl, unsigned NumVecs,
1603 unsigned NumVecs, bool is64BitVector) {
1604 unsigned NumRegs = NumVecs;
1605 if (!is64BitVector && NumVecs < 3)
1738 static bool isPerfectIncrement(SDValue Inc, EVT VecTy, unsigned NumVecs) {
1740 return C && C->getZExtValue() == VecTy.getSizeInBits() / 8 * NumVecs;
1743 void ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
1747 assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range");
1760 Align = GetVLDSTAlign(Align, dl, NumVecs, is64BitVector);
1781 if (NumVecs == 1)
1784 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1801 if (is64BitVector || NumVecs <= 2) {
1808 bool IsImmUpdate = isPerfectIncrement(Inc, VT, NumVecs);
1861 if (NumVecs == 1) {
1872 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1875 ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1));
1877 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLd, 2));
1881 void ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
1885 assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range");
1902 Align = GetVLDSTAlign(Align, dl, NumVecs, is64BitVector);
1934 if (is64BitVector || NumVecs <= 2) {
1936 if (NumVecs == 1) {
1942 if (NumVecs == 2)
1948 SDValue V3 = (NumVecs == 3)
1966 bool IsImmUpdate = isPerfectIncrement(Inc, VT, NumVecs);
1999 SDValue V3 = (NumVecs == 3)
2034 unsigned NumVecs,
2037 assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");
2053 cast<ConstantSDNode>(N->getOperand(Vec0Idx + NumVecs))->getZExtValue();
2058 if (NumVecs != 3) {
2060 unsigned NumBytes = NumVecs * VT.getScalarSizeInBits() / 8;
2088 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
2107 isPerfectIncrement(Inc, VT.getVectorElementType(), NumVecs);
2114 if (NumVecs == 2) {
2121 SDValue V3 = (NumVecs == 3)
2150 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
2153 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, 1));
2155 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdLn, 2));
2160 bool isUpdating, unsigned NumVecs,
2164 NumVecs >= 1 && NumVecs <= 4 && "VLDDup NumVecs out-of-range");
2177 if (NumVecs != 3) {
2179 unsigned NumBytes = NumVecs * VT.getScalarSizeInBits() / 8;
2206 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
2221 if (is64BitVector || NumVecs == 1) {
2232 isPerfectIncrement(Inc, VT.getVectorElementType(), NumVecs);
2233 if (NumVecs <= 2 && !IsImmUpdate)
2238 else if (NumVecs > 2)
2245 } else if (NumVecs == 2) {
2272 if (NumVecs == 1) {
2278 for (unsigned Vec = 0; Vec != NumVecs; ++Vec) {
2283 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdDup, 1));
2285 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdDup, 2));
