Lines Matching refs:PredReg
172 ARMCC::CondCodes Pred, unsigned PredReg);
176 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
181 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
485 unsigned PredReg) {
554 .addReg(PredReg);
575 .addReg(PredReg);
625 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
739 .add(predOps(Pred, PredReg));
750 .add(predOps(Pred, PredReg));
756 .add(predOps(Pred, PredReg));
761 .add(predOps(Pred, PredReg))
806 UpdateBaseRegUses(MBB, InsertBefore, DL, Base, NumRegs, Pred, PredReg);
813 MIB.addImm(Pred).addReg(PredReg);
824 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
840 MIB.addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);
892 unsigned PredReg = 0;
893 ARMCC::CondCodes Pred = getInstrPredicate(*First, PredReg);
898 Opcode, Pred, PredReg, DL, Regs);
901 Opcode, Pred, PredReg, DL, Regs);
1161 ARMCC::CondCodes Pred, unsigned PredReg) {
1180 MIPredReg != PredReg)
1191 ARMCC::CondCodes Pred, unsigned PredReg, int &Offset) {
1204 Offset = isIncrementOrDecrement(*PrevMBBI, Reg, Pred, PredReg);
1211 ARMCC::CondCodes Pred, unsigned PredReg, int &Offset) {
1222 Offset = isIncrementOrDecrement(*NextMBBI, Reg, Pred, PredReg);
1245 unsigned PredReg = 0;
1246 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);
1261 = findIncDecBefore(MBBI, Base, Pred, PredReg, Offset);
1268 MergeInstr = findIncDecAfter(MBBI, Base, Pred, PredReg, Offset);
1299 .addImm(Pred).addReg(PredReg);
1387 unsigned PredReg = 0;
1388 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);
1394 = findIncDecBefore(MBBI, Base, Pred, PredReg, Offset);
1401 MergeInstr = findIncDecAfter(MBBI, Base, Pred, PredReg, Offset);
1423 .addImm(Pred).addReg(PredReg)
1432 .addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);
1440 .add(predOps(Pred, PredReg));
1448 .add(predOps(Pred, PredReg));
1463 .add(predOps(Pred, PredReg));
1470 .add(predOps(Pred, PredReg));
1494 unsigned PredReg;
1495 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
1500 PredReg, Offset);
1505 MergeInstr = findIncDecAfter(MBBI, Base, Pred, PredReg, Offset);
1522 .addImm(Offset).addImm(Pred).addReg(PredReg);
1596 unsigned PredReg, const TargetInstrInfo *TII) {
1602 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
1608 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
1652 unsigned PredReg = 0;
1653 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);
1664 .addImm(Pred).addReg(PredReg)
1671 .addImm(Pred).addReg(PredReg)
1693 false, BaseReg, false, BaseUndef, Pred, PredReg, TII);
1695 false, BaseReg, BaseKill, BaseUndef, Pred, PredReg, TII);
1708 EvenUndef, BaseReg, false, BaseUndef, Pred, PredReg, TII);
1710 OddUndef, BaseReg, BaseKill, BaseUndef, Pred, PredReg, TII);
1747 unsigned PredReg = 0;
1748 ARMCC::CondCodes Pred = getInstrPredicate(*MBBI, PredReg);
1758 // Note: No need to match PredReg in the next if.
2021 unsigned &PredReg, ARMCC::CondCodes &Pred,
2099 unsigned &PredReg,
2163 Pred = getInstrPredicate(*Op0, PredReg);
2264 unsigned BaseReg = 0, PredReg = 0;
2272 Offset, PredReg, Pred, isT2)) {
2292 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
2306 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
2363 unsigned PredReg = 0;
2364 if (getInstrPredicate(MI, PredReg) != ARMCC::AL)
