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Lines Matching refs:PredReg

70   unsigned PredReg = 0;
71   ARMCC::CondCodes CC = getInstrPredicate(*Tail, PredReg);
118   unsigned PredReg = 0;
119   return getITInstrPredicate(*MBBI, PredReg) == ARMCC::AL;
240                                   ARMCC::CondCodes Pred, unsigned PredReg,
246       .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
263         .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
270         .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
279             .add(predOps(Pred, PredReg))
291             .add(predOps(Pred, PredReg))
491     unsigned PredReg;
492     if (Offset == 0 && getInstrPredicate(MI, PredReg) == ARMCC::AL &&
679                                            unsigned &PredReg) {
683   return getInstrPredicate(MI, PredReg);