Lines Matching defs:RR
182 bool operator== (RegisterRef RR) const {
183 return Reg == RR.Reg && Sub == RR.Sub;
185 bool operator!= (RegisterRef RR) const { return !operator==(RR); }
186 bool operator< (RegisterRef RR) const {
187 return Reg < RR.Reg || (Reg == RR.Reg && Sub < RR.Sub);
201 void addRefToMap(RegisterRef RR, ReferenceMap &Map, unsigned Exec);
235 bool isIntReg(RegisterRef RR, unsigned &BW);
294 void HexagonExpandCondsets::addRefToMap(RegisterRef RR, ReferenceMap &Map,
296 unsigned Mask = getMaskForSub(RR.Sub) | Exec;
297 ReferenceMap::iterator F = Map.find(RR.Reg);
299 Map.insert(std::make_pair(RR.Reg, Mask));
304 bool HexagonExpandCondsets::isRefInMap(RegisterRef RR, ReferenceMap &Map,
306 ReferenceMap::iterator F = Map.find(RR.Reg);
309 unsigned Mask = getMaskForSub(RR.Sub) | Exec;
768 RegisterRef RR = Op;
769 if (RR.Reg == PredR) {
773 if (RR.Reg != RD.Reg)
778 if (RR.Sub == RD.Sub)
780 if (RR.Sub == 0 || RD.Sub == 0)
802 RegisterRef RR = Op;
806 if (!TargetRegisterInfo::isVirtualRegister(RR.Reg))
809 if (isRefInMap(RR, Defs, Exec_Then))
812 if (Op.isDef() && isRefInMap(RR, Uses, Exec_Then))
1009 RegisterRef RR = Op;
1010 if (!TargetRegisterInfo::isVirtualRegister(RR.Reg))
1015 assert(RR.Sub && "Expecting a subregister on <def,read-undef>");
1019 RR.Sub = 0;
1021 addRefToMap(RR, Map, Exec);
1101 bool HexagonExpandCondsets::isIntReg(RegisterRef RR, unsigned &BW) {
1102 if (!TargetRegisterInfo::isVirtualRegister(RR.Reg))
1104 const TargetRegisterClass *RC = MRI->getRegClass(RR.Reg);
1110 BW = (RR.Sub != 0) ? 32 : 64;
