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Lines Matching refs:PredOp

215         unsigned DstSR, const MachineOperand &PredOp, bool PredSense,
226 const MachineOperand &PredOp, bool Cond,
621 /// PredOp. The Cond argument specifies whether the predicate is to be
622 /// if(PredOp), or if(!PredOp).
625 unsigned DstR, unsigned DstSR, const MachineOperand &PredOp,
639 unsigned PredState = getRegState(PredOp) & ~RegState::Kill;
648 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg())
653 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg())
857 const MachineOperand &PredOp, bool Cond,
886 MB.addReg(PredOp.getReg(), PredOp.isUndef() ? RegState::Undef : 0,
887 PredOp.getSubReg());