Lines Matching refs:TmpR
1549 unsigned TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1550 BuildMI(B, It, DL, HII.get(TargetOpcode::COPY), TmpR).add(MI->getOperand(1));
1552 .addReg(TmpR, RegState::Kill);
1554 NewRegs.push_back(TmpR);
1572 // TmpR = C2_tfrpr SrcR if SrcR is a predicate register
1573 // TmpR = A2_tfrcrr SrcR if SrcR is a modifier register
1574 unsigned TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1577 BuildMI(B, It, DL, HII.get(TfrOpc), TmpR)
1580 // S2_storeri_io FI, 0, TmpR
1584 .addReg(TmpR, RegState::Kill)
1587 NewRegs.push_back(TmpR);
1604 // TmpR = L2_loadri_io FI, 0
1605 unsigned TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1606 BuildMI(B, It, DL, HII.get(Hexagon::L2_loadri_io), TmpR)
1611 // DstR = C2_tfrrp TmpR if DstR is a predicate register
1612 // DstR = A2_tfrrcr TmpR if DstR is a modifier register
1616 .addReg(TmpR, RegState::Kill);
1618 NewRegs.push_back(TmpR);
