Lines Matching refs:IsLP64
46 IsLP64 = STI.isTarget64BitLP64();
96 static unsigned getSUBriOpcode(unsigned IsLP64, int64_t Imm) {
97 if (IsLP64) {
108 static unsigned getADDriOpcode(unsigned IsLP64, int64_t Imm) {
109 if (IsLP64) {
120 static unsigned getSUBrrOpcode(unsigned isLP64) {
121 return isLP64 ? X86::SUB64rr : X86::SUB32rr;
124 static unsigned getADDrrOpcode(unsigned isLP64) {
125 return isLP64 ? X86::ADD64rr : X86::ADD32rr;
128 static unsigned getANDriOpcode(bool IsLP64, int64_t Imm) {
129 if (IsLP64) {
139 static unsigned getLEArOpcode(unsigned IsLP64) {
140 return IsLP64 ? X86::LEA64r : X86::LEA32r;
2200 GetScratchRegister(bool Is64Bit, bool IsLP64, const MachineFunction &MF, bool Primary) {
2212 if (IsLP64)
2247 unsigned ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);
2287 allocMBB->addLiveIn(IsLP64 ? X86::R10 : X86::R10D);
2300 TlsOffset = IsLP64 ? 0x70 : 0x40;
2318 ScratchReg = IsLP64 ? X86::RSP : X86::ESP;
2320 BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::LEA64r : X86::LEA64_32r), ScratchReg).addReg(X86::RSP)
2323 BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::CMP64rm : X86::CMP32rm)).addReg(ScratchReg)
2361 ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, true);
2365 ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, false);
2403 const unsigned RegAX = IsLP64 ? X86::RAX : X86::EAX;
2404 const unsigned Reg10 = IsLP64 ? X86::R10 : X86::R10D;
2405 const unsigned Reg11 = IsLP64 ? X86::R11 : X86::R11D;
2406 const unsigned MOVrr = IsLP64 ? X86::MOV64rr : X86::MOV32rr;
2407 const unsigned MOVri = IsLP64 ? X86::MOV64ri : X86::MOV32ri;
2615 ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);
