Lines Matching refs:SBB
18780 SDValue Cmp = DAG.getNode(X86ISD::SBB, DL, VTs, LHS, RHS, Carry.getValue(1));
18792 Opc == X86ISD::SBB || Opc == X86ISD::SMUL ||
18962 // (select (x != 0), -1, 0) -> neg & sbb
18963 // (select (x == 0), 0, -1) -> neg & sbb
21692 // ADC/ADCX/SBB
24888 unsigned Opc = Op.getOpcode() == ISD::ADDCARRY ? X86ISD::ADC : X86ISD::SBB;
26029 case X86ISD::SBB: return "X86ISD::SBB";
38492 return DAG.getNode(X86ISD::SBB, SDLoc(N), VTs,
38534 /// Materialize "setb reg" as "sbb reg,reg", since it produces an all-ones bit
38540 SDValue SBB = DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8, CF, EFLAGS);
38543 return DAG.getNode(ISD::AND, DL, VT, SBB, DAG.getConstant(1, DL, VT));
38546 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SBB);
38550 /// then try to convert it to an ADC or SBB. This replaces TEST+SET+{ADD/SUB}
38551 /// with CMP+{ADC, SBB}.
38591 // -1 + SETAE --> -1 + (!CF) --> CF ? -1 : 0 --> SBB %eax, %eax
38592 // 0 - SETB --> 0 - (CF) --> CF ? -1 : 0 --> SBB %eax, %eax
38605 // -1 + SETBE (SUB A, B) --> -1 + SETAE (SUB B, A) --> SUB + SBB
38606 // 0 - SETA (SUB A, B) --> 0 - SETB (SUB B, A) --> SUB + SBB
38619 // X + SETB Z --> X + (mask SBB Z, Z)
38620 // X - SETB Z --> X - (mask SBB Z, Z)
38621 // TODO: Produce ADC/SBB here directly and avoid SETCC_CARRY?
38622 SDValue SBB = materializeSBB(Y.getNode(), Y.getOperand(1), DAG);
38623 if (SBB.getValueSizeInBits() != VT.getSizeInBits())
38624 SBB = DAG.getZExtOrTrunc(SBB, DL, VT);
38625 return DAG.getNode(IsSub ? ISD::SUB : ISD::ADD, DL, VT, X, SBB);
38643 SDValue SBB = materializeSBB(Y.getNode(), NewEFLAGS, DAG);
38644 if (SBB.getValueSizeInBits() != VT.getSizeInBits())
38645 SBB = DAG.getZExtOrTrunc(SBB, DL, VT);
38646 return DAG.getNode(IsSub ? ISD::SUB : ISD::ADD, DL, VT, X, SBB);
38665 // 'neg' sets the carry flag when Z != 0, so create 0 or -1 using 'sbb' with
38667 // 0 - (Z != 0) --> sbb %eax, %eax, (neg Z)
38668 // -1 + (Z == 0) --> sbb %eax, %eax, (neg Z)
38679 // cmp with 1 sets the carry flag when Z == 0, so create 0 or -1 using 'sbb'
38681 // 0 - (Z == 0) --> sbb %eax, %eax, (cmp Z, 1)
38682 // -1 + (Z != 0) --> sbb %eax, %eax, (cmp Z, 1)
38696 // Add the flags type for ADC/SBB nodes.
38700 // X + (Z != 0) --> add X, (zext(setne Z, 0)) --> sbb X, -1, (cmp Z, 1)
38702 return DAG.getNode(IsSub ? X86ISD::ADC : X86ISD::SBB, DL, VTs, X,
38705 // X - (Z == 0) --> sub X, (zext(sete Z, 0)) --> sbb X, 0, (cmp Z, 1)
38707 return DAG.getNode(IsSub ? X86ISD::SBB : X86ISD::ADC, DL, VTs, X,
39646 case X86ISD::SBB: return combineSBB(N, DAG);
