Lines Matching refs:SHLD
16185 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
16196 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
16204 // rely on the results of shld/shrd. Insert a test and select the appropriate
25898 case X86ISD::SHLD: return "X86ISD::SHLD";
35131 // SHLD/SHRD instructions have lower register pressure, but on some
35134 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
35158 unsigned Opc = X86ISD::SHLD;
35168 // OR( SHL( X, C ), SRL( Y, 32 - C ) ) -> SHLD( X, Y, C )
35170 // OR( SHL( X, C ), SRL( SRL( Y, 1 ), XOR( C, 31 ) ) ) -> SHLD( X, Y, C )
35195 unsigned InnerShift = (X86ISD::SHLD == Opc ? ISD::SRL : ISD::SHL);
