Home | History | Annotate | Download | only in X86

Lines Matching refs:isOperationLegalOrCustom

4700   if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
7264 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
8377 (isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT) ||
8378 isOperationLegalOrCustom(ISD::VECTOR_SHUFFLE, VT))) {
19592 assert(TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND_VECTOR_INREG, RegVT) &&
31379 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
32561 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))