Lines Matching defs:RegID
145 unsigned RegID = WS.getRegisterID();
146 assert(RegID && "Adding an invalid register definition?");
150 << ", " << MRI.getName(RegID) << "]\n";
153 // If RenameAs is equal to RegID, then RegID is subject to register renaming
154 // and false dependencies on RegID are all eliminated.
159 // cases, RenameAs must be either equal to RegID, or it must reference a
160 // super-register of RegID.
162 // If RenameAs is a super-register of RegID, then a write to RegID has always
166 const RegisterRenamingInfo &RRI = RegisterMappings[RegID].second;
167 if (RRI.RenameAs && RRI.RenameAs != RegID) {
168 RegID = RRI.RenameAs;
169 const WriteRef &OtherWrite = RegisterMappings[RegID].first;
172 // The processor keeps the definition of `RegID` together with register
184 // Update the mapping for register RegID including its sub-registers.
185 RegisterMappings[RegID].first = Write;
186 for (MCSubRegIterator I(RegID, &MRI); I.isValid(); ++I)
193 allocatePhysRegs(RegisterMappings[RegID].second, UsedPhysRegs);
198 for (MCSuperRegIterator I(RegID, &MRI); I.isValid(); ++I)
205 unsigned RegID = WS.getRegisterID();
207 assert(RegID != 0 && "Invalidating an already invalid register?");
212 unsigned RenameAs = RegisterMappings[RegID].second.RenameAs;
213 if (RenameAs && RenameAs != RegID) {
214 RegID = RenameAs;
217 // Keep the definition of `RegID` together with register `RenameAs`.
223 freePhysRegs(RegisterMappings[RegID].second, FreedPhysRegs);
225 WriteRef &WR = RegisterMappings[RegID].first;
229 for (MCSubRegIterator I(RegID, &MRI); I.isValid(); ++I) {
238 for (MCSuperRegIterator I(RegID, &MRI); I.isValid(); ++I) {
246 unsigned RegID) const {
247 assert(RegID && RegID < RegisterMappings.size());
249 << MRI.getName(RegID) << '\n');
250 const WriteRef &WR = RegisterMappings[RegID].first;
255 for (MCSubRegIterator I(RegID, &MRI); I.isValid(); ++I) {
283 for (const unsigned RegID : Regs) {
284 const RegisterRenamingInfo &RRI = RegisterMappings[RegID].second;
