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Lines Matching refs:ALT2

121 						ir = <&pio4 0 ALT2 IN>;
127 ir = <&pio4 1 ALT2 IN>;
133 tx = <&pio4 2 ALT2 OUT>;
139 tx_od = <&pio4 3 ALT2 OUT>;
186 keyin2 = <&pio0 4 ALT2 IN>;
187 keyin3 = <&pio2 6 ALT2 IN>;
190 keyout1 = <&pio1 7 ALT2 OUT>;
191 keyout2 = <&pio0 6 ALT2 OUT>;
192 keyout3 = <&pio2 7 ALT2 OUT>;
290 phyclk = <&pio2 3 ALT2 IN NICLK 0 CLK_A>;
338 pinctrl_spi11_default: spi11-4w-alt2-0 {
340 mtsr = <&pio3 1 ALT2 OUT>;
341 mrst = <&pio3 0 ALT2 IN>;
342 scl = <&pio3 2 ALT2 OUT>;
346 pinctrl_spi11_3w_alt2_0: spi11-3w-alt2-0 {
348 mtsr = <&pio3 1 ALT2 BIDIR_PU>;
349 scl = <&pio3 2 ALT2 OUT>;
355 pinctrl_spi12_default: spi12-4w-alt2-0 {
357 mtsr = <&pio3 6 ALT2 OUT>;
358 mrst = <&pio3 4 ALT2 IN>;
359 scl = <&pio3 7 ALT2 OUT>;
363 pinctrl_spi12_3w_alt2_0: spi12-3w-alt2-0 {
365 mtsr = <&pio3 6 ALT2 BIDIR_PU>;
366 scl = <&pio3 7 ALT2 OUT>;
524 sda = <&pio10 6 ALT2 BIDIR>;
525 scl = <&pio10 5 ALT2 BIDIR>;
533 sda = <&pio11 1 ALT2 BIDIR>;
534 scl = <&pio11 0 ALT2 BIDIR>;
542 sda = <&pio15 6 ALT2 BIDIR>;
543 scl = <&pio15 5 ALT2 BIDIR>;
547 pinctrl_i2c2_alt2_1: i2c2-alt2-1 {
549 sda = <&pio12 6 ALT2 BIDIR>;
550 scl = <&pio12 5 ALT2 BIDIR>;
577 pinctrl_spi0_default: spi0-4w-alt2-0 {
579 mtsr = <&pio10 6 ALT2 OUT>;
580 mrst = <&pio10 7 ALT2 IN>;
581 scl = <&pio10 5 ALT2 OUT>;
585 pinctrl_spi0_3w_alt2_0: spi0-3w-alt2-0 {
587 mtsr = <&pio10 6 ALT2 BIDIR_PU>;
588 scl = <&pio10 5 ALT2 OUT>;
609 pinctrl_spi1_default: spi1-4w-alt2-0 {
611 mtsr = <&pio11 1 ALT2 OUT>;
612 mrst = <&pio11 2 ALT2 IN>;
613 scl = <&pio11 0 ALT2 OUT>;
617 pinctrl_spi1_3w_alt2_0: spi1-3w-alt2-0 {
619 mtsr = <&pio11 1 ALT2 BIDIR_PU>;
620 scl = <&pio11 0 ALT2 OUT>;
641 pinctrl_spi2_default: spi2-4w-alt2-0 {
643 mtsr = <&pio12 6 ALT2 OUT>;
644 mrst = <&pio12 7 ALT2 IN>;
645 scl = <&pio12 5 ALT2 OUT>;
649 pinctrl_spi2_3w_alt2_0: spi2-3w-alt2-0 {
651 mtsr = <&pio12 6 ALT2 BIDIR_PU>;
652 scl = <&pio12 5 ALT2 OUT>;
671 pinctrl_spi2_4w_alt2_1: spi2-4w-alt2-1 {
673 mtsr = <&pio15 6 ALT2 OUT>;
674 mrst = <&pio15 7 ALT2 IN>;
675 scl = <&pio15 5 ALT2 OUT>;
679 pinctrl_spi2_3w_alt2_1: spi2-3w-alt2-1 {
681 mtsr = <&pio15 6 ALT2 BIDIR_PU>;
682 scl = <&pio15 5 ALT2 OUT>;
794 DATA6 = <&pio13 5 ALT2 IN SE_NICLK_IO 0 CLK_B>;
795 DATA5 = <&pio13 6 ALT2 IN SE_NICLK_IO 0 CLK_B>;
796 DATA4 = <&pio13 7 ALT2 IN SE_NICLK_IO 0 CLK_B>;
797 DATA3 = <&pio14 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
798 DATA2 = <&pio14 1 ALT2 IN SE_NICLK_IO 0 CLK_B>;
799 DATA1 = <&pio14 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
800 DATA0 = <&pio14 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
854 DATA7 = <&pio19 4 ALT2 IN SE_NICLK_IO 0 CLK_A>;
855 CLKIN = <&pio19 3 ALT2 IN CLKNOTDATA 0 CLK_A>;
856 VALID = <&pio19 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
857 ERROR = <&pio19 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
858 PKCLK = <&pio19 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
1032 hs = <&pio30 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1033 vs = <&pio30 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1034 de = <&pio30 2 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1035 ck = <&pio30 3 ALT2 (OE | CLKNOTDATA) 0>;
1036 d0 = <&pio30 4 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1037 d1 = <&pio30 5 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1038 d2 = <&pio30 6 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1039 d3 = <&pio30 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1040 d4 = <&pio31 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1041 d5 = <&pio31 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1042 d6 = <&pio31 2 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1043 d7 = <&pio31 3 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1044 d8 = <&pio31 4 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1045 d9 = <&pio31 5 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1046 d10 = <&pio31 6 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1047 d11 = <&pio31 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1048 d12 = <&pio32 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1049 d13 = <&pio32 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1050 d14 = <&pio32 2 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1051 d15 = <&pio32 3 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1052 d16 = <&pio32 4 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1053 d17 = <&pio32 5 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1054 d18 = <&pio32 6 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1055 d19 = <&pio32 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1056 d20 = <&pio33 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1057 d21 = <&pio33 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1058 d22 = <&pio33 2 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1059 d23 = <&pio33 3 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1257 sd_led = <&pio42 0 ALT2 OUT>;
1258 sd_pwren = <&pio42 2 ALT2 OUT>;
1259 sd_vsel = <&pio42 3 ALT2 OUT>;
1260 sd_cd = <&pio42 4 ALT2 IN>;
1261 sd_wp = <&pio42 5 ALT2 IN>;