Lines Matching defs:Address
29 typedef void *Address ;
38 #define PXA_CS1_PHYS 0x04000000 /* Small partition start address (64MB) */
39 #define PXA_CS1_LPHYS 0x30000000 /* Large partition start address (256MB) */
223 #define DDADR0 0x40000200 /* DMA Descriptor Address Register Channel 0 */
224 #define DSADR0 0x40000204 /* DMA Source Address Register Channel 0 */
225 #define DTADR0 0x40000208 /* DMA Target Address Register Channel 0 */
226 #define DCMD0 0x4000020c /* DMA Command Address Register Channel 0 */
227 #define DDADR1 0x40000210 /* DMA Descriptor Address Register Channel 1 */
228 #define DSADR1 0x40000214 /* DMA Source Address Register Channel 1 */
229 #define DTADR1 0x40000218 /* DMA Target Address Register Channel 1 */
230 #define DCMD1 0x4000021c /* DMA Command Address Register Channel 1 */
231 #define DDADR2 0x40000220 /* DMA Descriptor Address Register Channel 2 */
232 #define DSADR2 0x40000224 /* DMA Source Address Register Channel 2 */
233 #define DTADR2 0x40000228 /* DMA Target Address Register Channel 2 */
234 #define DCMD2 0x4000022c /* DMA Command Address Register Channel 2 */
235 #define DDADR3 0x40000230 /* DMA Descriptor Address Register Channel 3 */
236 #define DSADR3 0x40000234 /* DMA Source Address Register Channel 3 */
237 #define DTADR3 0x40000238 /* DMA Target Address Register Channel 3 */
238 #define DCMD3 0x4000023c /* DMA Command Address Register Channel 3 */
239 #define DDADR4 0x40000240 /* DMA Descriptor Address Register Channel 4 */
240 #define DSADR4 0x40000244 /* DMA Source Address Register Channel 4 */
241 #define DTADR4 0x40000248 /* DMA Target Address Register Channel 4 */
242 #define DCMD4 0x4000024c /* DMA Command Address Register Channel 4 */
243 #define DDADR5 0x40000250 /* DMA Descriptor Address Register Channel 5 */
244 #define DSADR5 0x40000254 /* DMA Source Address Register Channel 5 */
245 #define DTADR5 0x40000258 /* DMA Target Address Register Channel 5 */
246 #define DCMD5 0x4000025c /* DMA Command Address Register Channel 5 */
247 #define DDADR6 0x40000260 /* DMA Descriptor Address Register Channel 6 */
248 #define DSADR6 0x40000264 /* DMA Source Address Register Channel 6 */
249 #define DTADR6 0x40000268 /* DMA Target Address Register Channel 6 */
250 #define DCMD6 0x4000026c /* DMA Command Address Register Channel 6 */
251 #define DDADR7 0x40000270 /* DMA Descriptor Address Register Channel 7 */
252 #define DSADR7 0x40000274 /* DMA Source Address Register Channel 7 */
253 #define DTADR7 0x40000278 /* DMA Target Address Register Channel 7 */
254 #define DCMD7 0x4000027c /* DMA Command Address Register Channel 7 */
255 #define DDADR8 0x40000280 /* DMA Descriptor Address Register Channel 8 */
256 #define DSADR8 0x40000284 /* DMA Source Address Register Channel 8 */
257 #define DTADR8 0x40000288 /* DMA Target Address Register Channel 8 */
258 #define DCMD8 0x4000028c /* DMA Command Address Register Channel 8 */
259 #define DDADR9 0x40000290 /* DMA Descriptor Address Register Channel 9 */
260 #define DSADR9 0x40000294 /* DMA Source Address Register Channel 9 */
261 #define DTADR9 0x40000298 /* DMA Target Address Register Channel 9 */
262 #define DCMD9 0x4000029c /* DMA Command Address Register Channel 9 */
263 #define DDADR10 0x400002a0 /* DMA Descriptor Address Register Channel 10 */
264 #define DSADR10 0x400002a4 /* DMA Source Address Register Channel 10 */
265 #define DTADR10 0x400002a8 /* DMA Target Address Register Channel 10 */
266 #define DCMD10 0x400002ac /* DMA Command Address Register Channel 10 */
267 #define DDADR11 0x400002b0 /* DMA Descriptor Address Register Channel 11 */
268 #define DSADR11 0x400002b4 /* DMA Source Address Register Channel 11 */
269 #define DTADR11 0x400002b8 /* DMA Target Address Register Channel 11 */
270 #define DCMD11 0x400002bc /* DMA Command Address Register Channel 11 */
271 #define DDADR12 0x400002c0 /* DMA Descriptor Address Register Channel 12 */
272 #define DSADR12 0x400002c4 /* DMA Source Address Register Channel 12 */
273 #define DTADR12 0x400002c8 /* DMA Target Address Register Channel 12 */
274 #define DCMD12 0x400002cc /* DMA Command Address Register Channel 12 */
275 #define DDADR13 0x400002d0 /* DMA Descriptor Address Register Channel 13 */
276 #define DSADR13 0x400002d4 /* DMA Source Address Register Channel 13 */
277 #define DTADR13 0x400002d8 /* DMA Target Address Register Channel 13 */
278 #define DCMD13 0x400002dc /* DMA Command Address Register Channel 13 */
279 #define DDADR14 0x400002e0 /* DMA Descriptor Address Register Channel 14 */
280 #define DSADR14 0x400002e4 /* DMA Source Address Register Channel 14 */
281 #define DTADR14 0x400002e8 /* DMA Target Address Register Channel 14 */
282 #define DCMD14 0x400002ec /* DMA Command Address Register Channel 14 */
283 #define DDADR15 0x400002f0 /* DMA Descriptor Address Register Channel 15 */
284 #define DSADR15 0x400002f4 /* DMA Source Address Register Channel 15 */
285 #define DTADR15 0x400002f8 /* DMA Target Address Register Channel 15 */
286 #define DCMD15 0x400002fc /* DMA Command Address Register Channel 15 */
293 #define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */
296 #define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */
297 #define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */
1750 #define GPIO55_nPREG 55 /* Card Address bit 26 */
2103 #define FDADR0 0x44000200 /* DMA Channel 0 Frame Descriptor Address Register */
2104 #define FSADR0 0x44000204 /* DMA Channel 0 Frame Source Address Register */
2107 #define FDADR1 0x44000210 /* DMA Channel 1 Frame Descriptor Address Register */
2108 #define FSADR1 0x44000214 /* DMA Channel 1 Frame Source Address Register */
2276 #define CSADRCFG0 0x4A000080 /* Address Configuration for chip select 0 */
2277 #define CSADRCFG1 0x4A000084 /* Address Configuration for chip select 1 */
2278 #define CSADRCFG2 0x4A000088 /* Address Configuration for chip select 2 */
2279 #define CSADRCFG3 0x4A00008C /* Address Configuration for chip select 3 */
2280 #define CSADRCFG_P 0x4A000090 /* Address Configuration for pcmcia card interface */
2281 #define CSMSADRCFG 0x4A0000A0 /* Master Address Configuration Register */
2306 #define TAI 0x48100F00 /* TAI Tavor Address Isolation Register */
2509 #define FDADR2 0x44000220 /* DMA Channel 2 Frame Descriptor Address Register */
2510 #define FSADR2 0x44000224 /* DMA Channel 2 Frame Source Address Register */
2513 #define FDADR3 0x44000230 /* DMA Channel 3 Frame Descriptor Address Register */
2514 #define FSADR3 0x44000234 /* DMA Channel 3 Frame Source Address Register */
2517 #define FDADR4 0x44000240 /* DMA Channel 4 Frame Descriptor Address Register */
2518 #define FSADR4 0x44000244 /* DMA Channel 4 Frame Source Address Register */
2521 #define FDADR5 0x44000250 /* DMA Channel 5 Frame Descriptor Address Register */
2522 #define FSADR5 0x44000254 /* DMA Channel 5 Frame Source Address Register */
