Lines Matching refs:MPLL
125 if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL ||
195 case MPLL:
225 case MPLL:
256 case MPLL:
277 /* According to the user manual, in EVT1 MPLL and BPLL always gives
278 * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/
279 if (pllreg == MPLL || pllreg == BPLL) {
283 case MPLL:
314 case MPLL:
437 sclk = exynos5_get_pll_clk(MPLL);
528 sclk = exynos542x_get_pll_clk(MPLL);
652 MPLL);
667 sclk = get_pll_clk(MPLL);
683 sclk = get_pll_clk(MPLL);
713 sclk = get_pll_clk(MPLL);
759 sclk = get_pll_clk(MPLL);
795 sclk = get_pll_clk(MPLL);
933 sclk = get_pll_clk(MPLL);
975 sclk = get_pll_clk(MPLL);
1049 const int reg_map[] = {0, CPLL, DPLL, MPLL, SPLL, IPLL, EPLL,
