Lines Matching refs:clk_sel
322 static u32 get_standard_pll_sel_clk(u32 clk_sel)
326 switch (clk_sel & 0x3) {
349 unsigned int clk_sel, freq, reg, pred, podf;
352 clk_sel = MXC_CCM_CSCMR1_UART_CLK_SEL_RD(reg);
353 freq = get_standard_pll_sel_clk(clk_sel);
368 u32 ret_val = 0, pdf, pre_pdf, clk_sel, freq;
374 clk_sel = MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(cscmr1);
375 freq = get_standard_pll_sel_clk(clk_sel);
385 u32 clk_sel = 0, pred = 0, podf = 0, freq = 0;
391 clk_sel = MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_RD(cscmr1);
396 clk_sel = MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_RD(cscmr1);
414 freq = get_standard_pll_sel_clk(clk_sel) / ((pred + 1) * (podf + 1));
797 s32 shift = 0, clk_sel, div = 1;
808 clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
809 switch (clk_sel) {
