Lines Matching refs:mmdc0
19 struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
22 setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);
23 wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
25 setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);
26 wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
31 struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
40 writel(0x04008050, &mmdc0->mdscr);
41 wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0);
45 writel(0x04008058, &mmdc0->mdscr);
46 wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0);
52 struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
55 writel(0x800, &mmdc0->mpmur0);
106 struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
118 ldectrl[0] = readl(&mmdc0->mpwldectrl0);
119 ldectrl[1] = readl(&mmdc0->mpwldectrl1);
126 clrbits_le32(&mmdc0->mdpdc, 0xff00);
129 setbits_le32(&mmdc0->mapsr, 0x1);
137 esdmisc_val = readl(&mmdc0->mdref);
138 writel(0x0000C000, &mmdc0->mdref);
139 zq_val = readl(&mmdc0->mpzqhwctrl);
140 writel(zq_val & ~0x3, &mmdc0->mpzqhwctrl);
144 setbits_le32(&mmdc0->mdmisc, rwalat_max);
156 writel(0x00808231, &mmdc0->mdscr);
159 writel(0x00000001, &mmdc0->mpwlgcr);
165 wait_for_bit_le32(&mmdc0->mpwlgcr, 1 << 0, 0, 100, 0);
171 if (readl(&mmdc0->mpwlgcr) & 0x00000F00)
180 if ((readl(&mmdc0->mpwldectrl0) == 0x001F001F) &&
181 (readl(&mmdc0->mpwldectrl1) == 0x001F001F) &&
186 writel(ldectrl[0], &mmdc0->mpwldectrl0);
187 writel(ldectrl[1], &mmdc0->mpwldectrl1);
195 correct_mpwldectr_result(&mmdc0->mpwldectrl0);
196 correct_mpwldectr_result(&mmdc0->mpwldectrl1);
211 writel((ddr_mr1 << 16) + 0x8031, &mmdc0->mdscr);
214 writel(esdmisc_val, &mmdc0->mdref);
215 writel(zq_val, &mmdc0->mpzqhwctrl);
218 readl(&mmdc0->mpwldectrl0));
220 readl(&mmdc0->mpwldectrl1));
229 readl(&mmdc0->mpwldectrl0);
230 readl(&mmdc0->mpwldectrl1);
237 setbits_le32(&mmdc0->mdpdc, 0x00005500);
240 clrbits_le32(&mmdc0->mapsr, 0x1);
243 writel(0, &mmdc0->mdscr);
250 struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
265 cs0_enable_initial = readl(&mmdc0->mdctl) & 0x80000000;
266 cs1_enable_initial = readl(&mmdc0->mdctl) & 0x40000000;
269 clrbits_le32(&mmdc0->mdpdc, 0xff00);
272 setbits_le32(&mmdc0->mapsr, 0x1);
285 esdmisc_val = readl(&mmdc0->mdmisc);
287 setbits_le32(&mmdc0->mdmisc,
291 temp_ref = readl(&mmdc0->mdref);
292 writel(0x0000c000, &mmdc0->mdref);
299 writel(0x00008020, &mmdc0->mdscr);
301 writel(0x00008028, &mmdc0->mdscr);
304 wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0);
315 if ((readl(&mmdc0->mdmisc) & 0x00100000) == 0)
316 clrbits_le32(&mmdc0->mdctl, 1 << 30); /* clear SDE_1 */
318 clrbits_le32(&mmdc0->mdctl, 1 << 31); /* clear SDE_0 */
324 cs0_enable = readl(&mmdc0->mdctl) & 0x80000000;
325 cs1_enable = readl(&mmdc0->mdctl) & 0x40000000;
330 writel(pddword, &mmdc0->mppdcmpr1);
337 setbits_le32(&mmdc0->mpswdar0, 1);
338 wait_for_bit_le32(&mmdc0->mpswdar0, 1 << 0, 0, 100, 0);
344 writel(initdelay, &mmdc0->mprddlctl);
377 setbits_le32(&mmdc0->mpdgctrl0, 1 << 30);
382 setbits_le32(&mmdc0->mpdgctrl0, 5 << 28);
385 wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 28, 0, 100, 0);
392 if (readl(&mmdc0->mpdgctrl0) & 0x00001000)
399 clrbits_le32(&mmdc0->mpdgctrl0, 1 << 30);
408 modify_dg_result(&mmdc0->mpdghwst0, &mmdc0->mpdghwst1,
409 &mmdc0->mpdgctrl0);
410 modify_dg_result(&mmdc0->mpdghwst2, &mmdc0->mpdghwst3,
411 &mmdc0->mpdgctrl1);
441 writel(0x00000030, &mmdc0->mprddlhwctl);
449 wait_for_bit_le32(&mmdc0->mprddlhwctl, 1 << 4, 0, 100, 0);
452 if (readl(&mmdc0->mprddlhwctl) & 0x0000000f)
481 writel(initdelay, &mmdc0->mpwrdlctl);
495 writel(0x00000030, &mmdc0->mpwrdlhwctl);
503 wait_for_bit_le32(&mmdc0->mpwrdlhwctl, 1 << 4, 0, 100, 0);
506 if (readl(&mmdc0->mpwrdlhwctl) & 0x0000000f)
518 setbits_le32(&mmdc0->mdpdc, 0x00005500);
521 clrbits_le32(&mmdc0->mapsr, 0x1);
524 writel(esdmisc_val, &mmdc0->mdmisc);
539 setbits_le32(&mmdc0->mdctl, 1 << 30);
543 setbits_le32(&mmdc0->mdctl, 1 << 31);
546 writel(temp_ref, &mmdc0->mdref);
549 writel(0x0, &mmdc0->mdscr); /* CS0 */
552 wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 0, 100, 0);
560 debug("\tMPDGCTRL0 PHY0 = 0x%08X\n", readl(&mmdc0->mpdgctrl0));
561 debug("\tMPDGCTRL1 PHY0 = 0x%08X\n", readl(&mmdc0->mpdgctrl1));
567 debug("\tMPRDDLCTL PHY0 = 0x%08X\n", readl(&mmdc0->mprddlctl));
571 debug("\tMPWRDLCTL PHY0 = 0x%08X\n", readl(&mmdc0->mpwrdlctl));
581 debug("\tMPDGHWST0 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst0));
582 debug("\tMPDGHWST1 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst1));
583 debug("\tMPDGHWST2 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst2));
584 debug("\tMPDGHWST3 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst3));
996 volatile struct mmdc_p_regs *mmdc0;
1012 mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
1102 mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0;
1103 mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1;
1104 mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0;
1105 mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1;
1106 mmdc0->mprddlctl = calib->p0_mprddlctl;
1107 mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;
1108 mmdc0->mpzqlp2ctl = calib->mpzqlp2ctl;
1111 mmdc0->mprddqby0dl = 0x33333333;
1112 mmdc0->mprddqby1dl = 0x33333333;
1114 mmdc0->mprddqby2dl = 0x33333333;
1115 mmdc0->mprddqby3dl = 0x33333333;
1119 mmdc0->mpwrdqby0dl = 0xf3333333;
1120 mmdc0->mpwrdqby1dl = 0xf3333333;
1122 mmdc0->mpwrdqby2dl = 0xf3333333;
1123 mmdc0->mpwrdqby3dl = 0xf3333333;
1130 mmdc0->mpodtctrl = 0;
1134 mmdc0->mpmur0 = val;
1137 mmdc0->mdscr = (u32)(1 << 15); /* config request */
1140 mmdc0->mdcfg0 = (trfc << 24) | (txsr << 16) | (txp << 13) |
1142 mmdc0->mdcfg1 = (tras << 16) | (twr << 9) | (tmrd << 5) | twl;
1143 mmdc0->mdcfg2 = (trtp << 6) | (twtr << 3) | trrd;
1144 mmdc0->mdcfg3lp = (trc_lp << 16) | (trcd_lp << 8) |
1146 mmdc0->mdotc = 0;
1148 mmdc0->mdasp = cs0_end; /* CS addressing */
1151 mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) |
1156 mmdc0->mdor = (sysinfo->sde_to_rst << 8) |
1165 mmdc0->mdctl = (lpddr2_cfg->rowaddr - 11) << 24 | /* ROW */
1172 mmdc0->mpzqhwctrl = val;
1175 mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */
1181 mmdc0->mdscr = MR(63, 0, 3, cs);
1186 mmdc0->mdscr = MR(val, 0, 3, cs);
1189 mmdc0->mdscr = MR(val, 0, 3, cs);
1192 mmdc0->mdscr = MR(val, 0, 3, cs);
1195 mmdc0->mdscr = MR(val, 0, 3, cs);
1199 mmdc0->mdpdc = (tcke & 0x7) << 16 |
1205 mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */
1209 mmdc0->mpzqhwctrl = val;
1212 mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11);
1215 mmdc0->mdscr = 0x00000000;
1225 volatile struct mmdc_p_regs *mmdc0;
1240 mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
1386 mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0;
1387 mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1;
1388 mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0;
1389 mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1;
1390 mmdc0->mprddlctl = calib->p0_mprddlctl;
1391 mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;
1402 mmdc0->mprddqby0dl = 0x33333333;
1403 mmdc0->mprddqby1dl = 0x33333333;
1405 mmdc0->mprddqby2dl = 0x33333333;
1406 mmdc0->mprddqby3dl = 0x33333333;
1418 mmdc0->mpodtctrl = val;
1424 mmdc0->mpmur0 = val;
1429 mmdc0->mdscr = (u32)(1 << 15); /* config request */
1432 mmdc0->mdcfg0 = (trfc << 24) | (txs << 16) | (txp << 13) |
1434 mmdc0->mdcfg1 = (trcd << 29) | (trp << 26) | (trc << 21) |
1437 mmdc0->mdcfg2 = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd;
1438 mmdc0->mdotc = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) |
1440 mmdc0->mdasp = cs0_end; /* CS addressing */
1443 mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) |
1448 mmdc0->mdor = (txpr << 16) | (sysinfo->sde_to_rst << 8) |
1457 mmdc0->mdctl = (ddr3_cfg->rowaddr - 11) << 24 | /* ROW */
1464 mmdc0->mpzqhwctrl = val;
1469 mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */
1478 mmdc0->mdscr = MR(val, 2, 3, cs);
1481 mmdc0->mdscr = MR(0, 3, 3, cs);
1486 mmdc0->mdscr = MR(val, 1, 3, cs);
1493 mmdc0->mdscr = MR(val, 0, 3, cs);
1496 mmdc0->mdscr = MR(val, 0, 4, cs);
1500 mmdc0->mdpdc = (tcke & 0x7) << 16 |
1507 mmdc0->mdpdc |= (1 << 7); /* SLOW_PD */
1508 mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */
1512 mmdc0->mpzqhwctrl = val;
1517 mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11);
1520 mmdc0->mdscr = 0x00000000;
1529 struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
1532 calib->p0_mpwldectrl0 = readl(&mmdc0->mpwldectrl0);
1533 calib->p0_mpwldectrl1 = readl(&mmdc0->mpwldectrl1);
1534 calib->p0_mpdgctrl0 = readl(&mmdc0->mpdgctrl0);
1535 calib->p0_mpdgctrl1 = readl(&mmdc0->mpdgctrl1);
1536 calib->p0_mprddlctl = readl(&mmdc0->mprddlctl);
1537 calib->p0_mpwrdlctl = readl(&mmdc0->mpwrdlctl);
