Lines Matching refs:mmdc1
53 struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
57 writel(0x800, &mmdc1->mpmur0);
107 struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
121 ldectrl[2] = readl(&mmdc1->mpwldectrl0);
122 ldectrl[3] = readl(&mmdc1->mpwldectrl1);
146 setbits_le32(&mmdc1->mdmisc, rwalat_max);
174 if (readl(&mmdc1->mpwlgcr) & 0x00000F00)
183 ((readl(&mmdc1->mpwldectrl0) == 0x001F001F) &&
184 (readl(&mmdc1->mpwldectrl1) == 0x001F001F)))) {
189 writel(ldectrl[2], &mmdc1->mpwldectrl0);
190 writel(ldectrl[3], &mmdc1->mpwldectrl1);
198 correct_mpwldectr_result(&mmdc1->mpwldectrl0);
199 correct_mpwldectr_result(&mmdc1->mpwldectrl1);
223 readl(&mmdc1->mpwldectrl0));
225 readl(&mmdc1->mpwldectrl1));
232 readl(&mmdc1->mpwldectrl0);
233 readl(&mmdc1->mpwldectrl1);
251 struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
346 writel(initdelay, &mmdc1->mprddlctl);
379 setbits_le32(&mmdc1->mpdgctrl0, 1 << 30);
395 if ((sysinfo->dsize == 0x2) && (readl(&mmdc1->mpdgctrl0) & 0x00001000))
401 clrbits_le32(&mmdc1->mpdgctrl0, 1 << 30);
413 modify_dg_result(&mmdc1->mpdghwst0, &mmdc1->mpdghwst1,
414 &mmdc1->mpdgctrl0);
415 modify_dg_result(&mmdc1->mpdghwst2, &mmdc1->mpdghwst3,
416 &mmdc1->mpdgctrl1);
456 (readl(&mmdc1->mprddlhwctl) & 0x0000000f))
483 writel(initdelay, &mmdc1->mpwrdlctl);
510 (readl(&mmdc1->mpwrdlhwctl) & 0x0000000f))
563 debug("\tMPDGCTRL0 PHY1 = 0x%08X\n", readl(&mmdc1->mpdgctrl0));
564 debug("\tMPDGCTRL1 PHY1 = 0x%08X\n", readl(&mmdc1->mpdgctrl1));
569 debug("\tMPRDDLCTL PHY1 = 0x%08X\n", readl(&mmdc1->mprddlctl));
573 debug("\tMPWRDLCTL PHY1 = 0x%08X\n", readl(&mmdc1->mpwrdlctl));
586 debug("\tMPDGHWST0 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst0));
587 debug("\tMPDGHWST1 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst1));
588 debug("\tMPDGHWST2 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst2));
589 debug("\tMPDGHWST3 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst3));
933 #define MMDC1(entry, value) do { \
935 mmdc1->entry = value; \
1226 volatile struct mmdc_p_regs *mmdc1;
1242 mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
1393 MMDC1(mpwldectrl0, calib->p1_mpwldectrl0);
1394 MMDC1(mpwldectrl1, calib->p1_mpwldectrl1);
1395 MMDC1(mpdgctrl0, calib->p1_mpdgctrl0);
1396 MMDC1(mpdgctrl1, calib->p1_mpdgctrl1);
1397 MMDC1(mprddlctl, calib->p1_mprddlctl);
1398 MMDC1(mpwrdlctl, calib->p1_mpwrdlctl);
1410 MMDC1(mprddqby0dl, 0x33333333);
1411 MMDC1(mprddqby1dl, 0x33333333);
1412 MMDC1(mprddqby2dl, 0x33333333);
1413 MMDC1(mprddqby3dl, 0x33333333);
1420 MMDC1(mpodtctrl, val);
1426 MMDC1(mpmur0, val);
1466 MMDC1(mpzqhwctrl, val);
1514 MMDC1(mpzqhwctrl, val);
1530 struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
1540 calib->p1_mpwldectrl0 = readl(&mmdc1->mpwldectrl0);
1541 calib->p1_mpwldectrl1 = readl(&mmdc1->mpwldectrl1);
1542 calib->p1_mpdgctrl0 = readl(&mmdc1->mpdgctrl0);
1543 calib->p1_mpdgctrl1 = readl(&mmdc1->mpdgctrl1);
1544 calib->p1_mprddlctl = readl(&mmdc1->mprddlctl);
1545 calib->p1_mpwrdlctl = readl(&mmdc1->mpwrdlctl);
