Home | History | Annotate | Download | only in mx7

Lines Matching refs:PLL_ENET

143 	case PLL_ENET:
144 reg = readl(&ccm_anatop->pll_enet);
299 freq = decode_pll(PLL_ENET, MXC_HCLK);
300 reg = readl(&ccm_anatop->pll_enet);
332 printf("Error derived pll_enet clock %d\n", derive);
366 case PLL_ENET:
407 return mxc_get_pll_derive(PLL_ENET, root_src);
743 reg = readl(&ccm_anatop->pll_enet);
744 /* If pll_enet powered up, no need to set it again */
747 writel(reg, &ccm_anatop->pll_enet);
750 if (readl(&ccm_anatop->pll_enet) & ANADIG_PLL_LOCK)
755 /* If timeout, we set pwdn for pll_enet. */
1032 /* Rom has enabled PLL_ARM, PLL_DDR, PLL_SYS, PLL_ENET
1109 freq = decode_pll(PLL_ENET, MXC_HCLK);