Lines Matching refs:para
561 static unsigned long dramc_init_helper(struct dram_para *para)
572 if (para->type != DRAM_MEMORY_TYPE_DDR3 || para->rank_num != 1)
576 mctl_setup_dram_clock(para->clock, para->mbus_clock);
592 mctl_enable_dll0(para->tpr3);
596 reg_val |= DRAM_DCR_IO_WIDTH(para->io_width >> 3);
598 if (para->density == 256)
600 else if (para->density == 512)
602 else if (para->density == 1024)
604 else if (para->density == 2048)
606 else if (para->density == 4096)
608 else if (para->density == 8192)
614 reg_val |= DRAM_DCR_BUS_WIDTH((para->bus_width >> 3) - 1);
615 reg_val |= DRAM_DCR_RANK_SEL(para->rank_num - 1);
622 mctl_set_impedance(para->zq, para->odt_en);
632 mctl_enable_dllx(para->tpr3);
635 dramc_set_autorefresh_cycle(para->clock, density);
638 writel(para->tpr0, &dram->tpr0);
639 writel(para->tpr1, &dram->tpr1);
640 writel(para->tpr2, &dram->tpr2);
646 reg_val |= DRAM_MR_CAS_LAT(para->cas - 4);
647 reg_val |= DRAM_MR_WRITE_RECOVERY(ddr3_write_recovery(para->clock));
650 writel(para->emr1, &dram->emr);
651 writel(para->emr2, &dram->emr2);
652 writel(para->emr3, &dram->emr3);
659 if (para->tpr4 & 0x1)
675 if (para->dqs_gating_delay)
676 mctl_set_dqs_gating_delay(0, para->dqs_gating_delay);
679 if (para->active_windowing)
692 unsigned long dramc_init(struct dram_para *para)
697 if (!para)
701 if (para->io_width && para->bus_width && para->density)
702 return dramc_init_helper(para);
705 para->io_width = 16;
706 para->bus_width = 32;
709 para->density = 4096;
712 para->density = 8192;
715 dram_size = dramc_init_helper(para);
718 para->bus_width = 16;
719 dram_size = dramc_init_helper(para);
727 actual_density = (dram_size >> 17) * para->io_width / para->bus_width;
729 if (actual_density != para->density) {
731 para->density = actual_density;
732 dram_size = dramc_init_helper(para);
