Cross Reference: /external/u-boot/arch/arm/mach-sunxi/dram_sun8i

Lines Matching refs:para
32 static void mctl_set_cr(struct dram_para *para)
37 	writel(MCTL_CR_CS1_CONTROL(para->cs1) | MCTL_CR_UNKNOWN |
39 	       (para->seq ? MCTL_CR_SEQUENCE : 0) |
40 	       ((para->bus_width == 16) ? MCTL_CR_BUSW16 : MCTL_CR_BUSW8) |
41 	       MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) |
42 	       MCTL_CR_BANK(para->bank) | MCTL_CR_RANK(para->rank),
46 static void auto_detect_dram_size(struct dram_para *para)
48 	u8 orig_rank = para->rank;
52 	para->page_size = 512;
53 	para->seq = 1;
54 	para->rows = 16;
55 	para->rank = 1;
56 	mctl_set_cr(para);
63 	para->rows = 11;
64 	para->page_size = 8192;
65 	mctl_set_cr(para);
71 	para->seq = 0;
72 	para->rank = orig_rank;
73 	para->rows = rows;
74 	para->page_size = 1 << columns;
75 	mctl_set_cr(para);
86 static void auto_set_timing_para(struct dram_para *para)
131 	mctl_set_cr(para);
179 static void mctl_data_train_cfg(struct dram_para *para)
184 	if (para->rank == 2)
190 static int mctl_train_dram(struct dram_para *para)
195 	mctl_data_train_cfg(para);
201 static int mctl_channel_init(struct dram_para *para)
210 	auto_set_timing_para(para);
231 	para->cs1 = 0;
232 	para->rank = 2;
233 	para->bus_width = 16;
234 	mctl_set_cr(para);
240 	mctl_data_train_cfg(para);
251 	if (mctl_train_dram(para) != 0) {
259 		para->rank = 1;
260 		mctl_set_cr(para);
267 			para->cs1 = 1;
268 			mctl_set_cr(para);
269 			if (mctl_train_dram(para) == 0)
275 		para->cs1 = 0;
276 		para->bus_width = 8;
277 		mctl_set_cr(para);
278 		if (mctl_train_dram(para) != 0)
294 static void mctl_sys_init(struct dram_para *para)
334 	struct dram_para para = {
343 	mctl_sys_init(&para);
345 	if (mctl_channel_init(&para) != 0)
348 	auto_detect_dram_size(&para);
354 	if (para.rank == 2)
359 	return para.page_size * (para.bus_width / 8) *
360 		(1 << (para.bank + para.rank + para.rows));
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