Lines Matching refs:para
213 if ((para->dram_clk <= 400)|((para->dram_tpr8 & 0x1)==0)) {
216 ccm_setup_pll6_ddr_clk((1000000 * (para->dram_clk) * 2), 0);
219 ccm_setup_pll6_ddr_clk((1000000 * (para->dram_clk) / 2), 1);
222 if (para->dram_tpr13 & (0xf<<18)) {
234 if(para->dram_tpr13 & (0x1<<18))
240 else if(para->dram_tpr13 & (0x1<<19))
246 else if(para->dram_tpr13 & (0x1<<20))
252 else if(para->dram_tpr13 & (0x1<<21))
307 if ((para->dram_clk <= 400) | ((para->dram_tpr8 & 0x1) == 0)) {
334 /* TODO if (para->chan == 2) */
338 static void mctl_com_init(struct dram_sun9i_para *para)
344 writel(((para->chan == 2) ? MCTL_CR_CHANNEL_DUAL :
347 | MCTL_CR_ROW(para->rows)
348 | ((para->bus_width == 32) ? MCTL_CR_BUSW32 : MCTL_CR_BUSW16)
349 | MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_RANK(para->rank),
355 static u32 mctl_channel_init(u32 ch_index, struct dram_sun9i_para *para)
374 /* const u32 tREFI = NS2CYCLES_FLOOR(para->tREFI); */
375 const u32 tREFI = NS2CYCLES_FLOOR(para->tREFI);
376 const u32 tRFC = NS2CYCLES_ROUNDUP(para->tRFC);
377 const u32 tRCD = PS2CYCLES_ROUNDUP(para->tRCD);
378 const u32 tRP = PS2CYCLES_ROUNDUP(para->tRP);
379 const u32 tRC = PS2CYCLES_ROUNDUP(para->tRC);
380 const u32 tRAS = PS2CYCLES_ROUNDUP(para->tRAS);
383 const u32 tDLLK = para->tDLLK;
384 const u32 tRTP = MAX(para->tRTP.ck, PS2CYCLES_ROUNDUP(para->tRTP.ps));
385 const u32 tWTR = MAX(para->tWTR.ck, PS2CYCLES_ROUNDUP(para->tWTR.ps));
386 const u32 tWR = NS2CYCLES_FLOOR(para->tWR);
387 const u32 tMRD = para->tMRD;
388 const u32 tMOD = MAX(para->tMOD.ck, PS2CYCLES_ROUNDUP(para->tMOD.ps));
389 const u32 tCCD = para->tCCD;
390 const u32 tRRD = MAX(para->tRRD.ck, PS2CYCLES_ROUNDUP(para->tRRD.ps));
391 const u32 tFAW = PS2CYCLES_ROUNDUP(para->tFAW);
394 /* const u32 tZQinit = MAX(para->tZQinit.ck,
395 PS2CYCLES_ROUNDUP(para->tZQinit.ps)); */
396 const u32 tZQoper = MAX(para->tZQoper.ck,
397 PS2CYCLES_ROUNDUP(para->tZQoper.ps));
398 const u32 tZQCS = MAX(para->tZQCS.ck,
399 PS2CYCLES_ROUNDUP(para->tZQCS.ps));
402 /* const u32 tXPR = MAX(para->tXPR.ck,
403 PS2CYCLES_ROUNDUP(para->tXPR.ps)); */
406 const u32 tXP = MAX(para->tXP.ck, PS2CYCLES_ROUNDUP(para->tXP.ps));
407 const u32 tXPDLL = MAX(para->tXPDLL.ck,
408 PS2CYCLES_ROUNDUP(para->tXPDLL.ps));
409 const u32 tCKE = MAX(para->tCKE.ck, PS2CYCLES_ROUNDUP(para->tCKE.ps));
415 const u32 tXS = MAX(para->tXS.ck, PS2CYCLES_ROUNDUP(para->tXS.ps));
416 const u32 tXSDLL = para->tXSDLL;
417 const u32 tCKSRE = MAX(para->tCKSRE.ck,
418 PS2CYCLES_ROUNDUP(para->tCKSRE.ps));
420 const u32 tCKSRX = MAX(para->tCKSRX.ck,
421 PS2CYCLES_ROUNDUP(para->tCKSRX.ps));
424 const u32 tWLMRD = para->tWLMRD;
425 /* const u32 tWLDQSEN = para->tWLDQSEN; */
426 const u32 tWLO = PS2CYCLES_FLOOR(para->tWLO);
427 /* const u32 tWLOE = PS2CYCLES_FLOOR(para->tWLOE); */
432 for (i = 0; i < para->cl_cwl_numentries; ++i) {
435 if ((para->cl_cwl_table[i].tCKmin <= tCK) &&
436 (tCK < para->cl_cwl_table[i].tCKmax)) {
437 CL = para->cl_cwl_table[i].CL;
438 CWL = para->cl_cwl_table[i].CWL;
459 if (para->dram_type == DRAM_TYPE_DDR3) {
572 if (para->dram_type == DRAM_TYPE_DDR3) {
592 writel(MCTL_MSTR_DEVICETYPE(para->dram_type) |
593 MCTL_MSTR_BURSTLENGTH(para->dram_type) |
594 MCTL_MSTR_ACTIVERANKS(para->rank) |
598 if (para->dram_type == DRAM_TYPE_DDR3) {
629 if (para->dram_type != DRAM_TYPE_DDR3)
663 if (para->dram_type == DRAM_TYPE_DDR3) {
688 writel(MCTL_DTCR_DEFAULT | MCTL_DTCR_RANKEN(para->rank),
717 if (para->dram_type == DRAM_TYPE_DDR3)
749 if (para->dram_type == DRAM_TYPE_DDR3)
769 if ((para->dram_type) == 6 || (para->dram_type) == 7) {
778 if (para->dram_tpr13 & (0x1<<31)) {
868 struct dram_sun9i_para para = {
942 if (!mctl_channel_init(0, ¶))
946 if (!mctl_channel_init(1, ¶)) {
954 mctl_com_init(¶);
