Lines Matching defs:source
163 void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
172 value |= source << OUT_CLK_SOURCE_31_30_SHIFT;
181 unsigned source)
188 source << OUT_CLK_SOURCE_31_30_SHIFT);
193 source << OUT_CLK_SOURCE_31_29_SHIFT);
198 source << OUT_CLK_SOURCE_31_28_SHIFT);
231 void clock_ll_set_source(enum periph_id periph_id, unsigned source)
233 clock_ll_set_source_bits(periph_id, MASK_BITS_31_30, source);
397 * Adjust peripheral PLL to use the given divider and source.
400 * @param source Source number (0-3 or 0-7)
406 static int adjust_periph_pll(enum periph_id periph_id, int source,
415 /* work out the source clock and set it */
416 if (source < 0)
419 clock_ll_set_source_bits(periph_id, mux_bits, source);
428 int source;
434 source = clock_ll_get_source_bits(periph_id, mux_bits);
436 return get_periph_clock_id(periph_id, source);
443 int mux_bits, divider_bits, source;
447 /* work out the source clock and set it */
448 source = get_periph_clock_source(periph_id, parent, &mux_bits,
457 if (adjust_periph_pll(periph_id, source, mux_bits, divider))
711 int source, mux_bits, divider_bits;
716 source = get_periph_clock_source(periph_id, parent, &mux_bits,
718 clock_ll_set_source_bits(periph_id, mux_bits, source);
749 * run up to 275MHz. On power on, the default sytem clock source is set
