Lines Matching defs:ohci
3 * URB OHCI HCD (Host Controller Driver) for USB on the AU1x00.
102 static u32 roothub_a (struct ohci *hc)
104 static inline u32 roothub_b (struct ohci *hc)
106 static inline u32 roothub_status (struct ohci *hc)
108 static u32 roothub_portstatus (struct ohci *hc, int i)
190 void ep_print_int_eds (ohci_t *ohci, char * str) {
195 ed_p = &(ohci->hcca->int_table [i]);
355 dbg ("OHCI controller usb-%s state", controller->slot_name);
377 ohci_t *ohci;
382 ohci = &gohci;
386 if (ohci->disabled) {
440 ep_link (ohci, ed);
455 ohci_t *ohci = &gohci;
457 return m16_swap (ohci->hcca->frame_no);
467 static int ep_link (ohci_t *ohci, ed_t *edi)
476 if (ohci->ed_controltail == NULL) {
477 writel ((long)ed, &ohci->regs->ed_controlhead);
479 ohci->ed_controltail->hwNextED = m32_swap (ed);
481 ed->ed_prev = ohci->ed_controltail;
482 if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
483 !ohci->ed_rm_list[1] && !ohci->sleeping) {
484 ohci->hc_control |= OHCI_CTRL_CLE;
485 writel (ohci->hc_control, &ohci->regs->control);
487 ohci->ed_controltail = edi;
492 if (ohci->ed_bulktail == NULL) {
493 writel ((long)ed, &ohci->regs->ed_bulkhead);
495 ohci->ed_bulktail->hwNextED = m32_swap (ed);
497 ed->ed_prev = ohci->ed_bulktail;
498 if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
499 !ohci->ed_rm_list[1] && !ohci->sleeping) {
500 ohci->hc_control |= OHCI_CTRL_BLE;
501 writel (ohci->hc_control, &ohci->regs->control);
503 ohci->ed_bulktail = edi;
516 static int ep_unlink (ohci_t *ohci, ed_t *ed)
524 ohci->hc_control &= ~OHCI_CTRL_CLE;
525 writel (ohci->hc_control, &ohci->regs->control);
527 writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead);
531 if (ohci->ed_controltail == ed) {
532 ohci->ed_controltail = ed->ed_prev;
541 ohci->hc_control &= ~OHCI_CTRL_BLE;
542 writel (ohci->hc_control, &ohci->regs->control);
544 writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead);
548 if (ohci->ed_bulktail == ed) {
549 ohci->ed_bulktail = ed->ed_prev;
608 /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
610 static void td_fill (ohci_t *ohci, unsigned int info,
666 ohci_t *ohci = &gohci;
673 /* OHCI handles the DATA-toggles itself, we just use the
692 td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);
697 td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);
700 if (!ohci->sleeping)
701 writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */
706 td_fill (ohci, info, kseg_to_phys(setup), 8, dev, cnt++, urb);
711 td_fill (ohci, info, data, data_len, dev, cnt++, urb);
715 td_fill (ohci, info, data, 0, dev, cnt++, urb);
716 if (!ohci->sleeping)
717 writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */
757 static td_t * dl_reverse_done_list (ohci_t *ohci)
764 td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0;
765 ohci->hcca->done_head = 0;
795 static int dl_done_list (ohci_t *ohci, td_t *td_list)
828 ep_unlink (ohci, ed);
1245 static int hc_reset (ohci_t *ohci)
1250 if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
1251 writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */
1253 while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
1263 writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);
1266 ohci->slot_name,
1267 readl (&ohci->regs->control));
1270 writel (0, &ohci->regs->control);
1273 writel (OHCI_HCR, &ohci->regs->cmdstatus);
1274 while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
1286 /* Start an OHCI controller, set the BUS operational
1290 static int hc_start (ohci_t * ohci)
1295 ohci->disabled = 1;
1300 writel (0, &ohci->regs->ed_controlhead);
1301 writel (0, &ohci->regs->ed_bulkhead);
1303 writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
1306 writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
1308 writel (fminterval, &ohci->regs->fminterval);
1309 writel (0x628, &ohci->regs->lsthresh);
1312 ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
1313 ohci->disabled = 0;
1314 writel (ohci->hc_control, &ohci->regs->control);
1320 writel (mask, &ohci->regs->intrdisable);
1323 writel (mask, &ohci->regs->intrstatus);
1326 writel (mask, &ohci->regs->intrenable);
1330 writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM,
1331 &ohci->regs->roothub.a);
1332 writel (RH_HS_LPSC, &ohci->regs->roothub.status);
1336 mdelay ((roothub_a (ohci) >> 23) & 0x1fe);
1339 ohci->rh.devnum = 0;
1351 ohci_t *ohci = &gohci;
1352 struct ohci_regs *regs = ohci->regs;
1356 if ((ohci->hcca->done_head != 0) && !(m32_swap (ohci->hcca->done_head) & 0x01)) {
1362 /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */
1369 ohci->disabled++;
1370 err ("OHCI Unrecoverable Error, controller usb-%s disabled",
1371 ohci->slot_name);
1375 ohci_dump (ohci, 1);
1383 hc_reset (ohci);
1402 unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1;
1405 if (ohci->ed_rm_list[frame] != NULL)
1420 static void hc_release_ohci (ohci_t *ohci)
1422 dbg ("USB HC release ohci usb-%s", ohci->slot_name);
1424 if (!ohci->disabled)
1425 hc_reset (ohci);
1493 printf("Au1000: 48MHz OHCI workaround enabled\n");
1516 dbg("OHCI board setup complete\n");
1529 dbg("OHCI clock running\n");
1563 dbg("OHCI revision: 0x%08x\n"
1587 err("OHCI initialization error\n");
