Lines Matching refs:gohci
74 static ohci_t gohci;
382 ohci = &gohci;
455 ohci_t *ohci = &gohci;
666 ohci_t *ohci = &gohci;
849 #define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}
850 #define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}
852 #define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status)
853 #define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
855 #define RD_RH_STAT roothub_status(&gohci)
856 #define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1)
989 case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);
1033 __u32 temp = roothub_a (&gohci);
1049 temp = roothub_b (&gohci);
1074 ohci_dump_roothub (&gohci, 1);
1131 /* ohci_dump_status(&gohci); */
1164 ohci_dump_roothub (&gohci, 1);
1168 timeout = rh_check_port_status(&gohci);
1172 usb_hub_port_connect_change(gohci.rh.dev, timeout - 1);
1222 if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
1223 gohci.rh.dev = dev;
1351 ohci_t *ohci = &gohci;
1390 stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));
1531 memset (&gohci, 0, sizeof (ohci_t));
1552 gohci.hcca = phcca;
1555 gohci.disabled = 1;
1556 gohci.sleeping = 0;
1557 gohci.irq = -1;
1558 gohci.regs = (struct ohci_regs *)(USB_OHCI_BASE | 0xA0000000);
1560 gohci.flags = 0;
1561 gohci.slot_name = "au1x00";
1565 readl(&gohci.regs->revision),
1566 readl(&gohci.regs->roothub.a), readl(&gohci.regs->roothub.b));
1568 if (hc_reset (&gohci) < 0)
1572 writel (gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control);
1575 if (hc_start (&gohci) < 0)
1579 ohci_dump (&gohci, 1);
1588 hc_release_ohci (&gohci);
1602 hc_reset (&gohci);
