Lines Matching defs:tx
174 u32 tx; /* eSPI transmit FIFO access */
351 u32 tctrl; /* TX Control */
352 u32 tstat; /* TX Status */
354 u32 tbdlen; /* TX Buffer Desc Data Len */
356 u32 ctbptrh; /* Current TX Buffer Desc Ptr High */
357 u32 ctbptr; /* Current TX Buffer Desc Ptr */
359 u32 tbptrh; /* TX Buffer Desc Ptr High */
360 u32 tbptr; /* TX Buffer Desc Ptr Low */
362 u32 tbaseh; /* TX Desc Base Addr High */
363 u32 tbase; /* TX Desc Base Addr */
365 u32 ostbd; /* Out-of-Sequence(OOS) TX Buffer Desc */
366 u32 ostbdp; /* OOS TX Data Buffer Ptr */
367 u32 os32tbdp; /* OOS 32 Bytes TX Data Buffer Ptr Low */
368 u32 os32iptrh; /* OOS 32 Bytes TX Insert Ptr High */
369 u32 os32iptrl; /* OOS 32 Bytes TX Insert Ptr Low */
370 u32 os32tbdr; /* OOS 32 Bytes TX Reserved */
371 u32 os32iil; /* OOS 32 Bytes TX Insert Idx/Len */
419 u32 tr64; /* TX & RX 64-byte Frame Counter */
420 u32 tr127; /* TX & RX 65-127 byte Frame Counter */
421 u32 tr255; /* TX & RX 128-255 byte Frame Counter */
422 u32 tr511; /* TX & RX 256-511 byte Frame Counter */
423 u32 tr1k; /* TX & RX 512-1023 byte Frame Counter */
424 u32 trmax; /* TX & RX 1024-1518 byte Frame Counter */
425 u32 trmgv; /* TX & RX 1519-1522 byte Good VLAN Frame */
443 u32 tbyt; /* TX Byte Counter Counter */
444 u32 tpkt; /* TX Packet Counter */
445 u32 tmca; /* TX Multicast Packet Counter */
446 u32 tbca; /* TX Broadcast Packet Counter */
447 u32 txpf; /* TX Pause Control Frame Counter */
448 u32 tdfr; /* TX Deferral Packet Counter */
449 u32 tedf; /* TX Excessive Deferral Packet Counter */
450 u32 tscl; /* TX Single Collision Packet Counter */
451 u32 tmcl; /* TX Multiple Collision Packet Counter */
452 u32 tlcl; /* TX Late Collision Packet Counter */
453 u32 txcl; /* TX Excessive Collision Packet Counter */
454 u32 tncl; /* TX Total Collision Counter */
456 u32 tdrp; /* TX Drop Frame Counter */
457 u32 tjbr; /* TX Jabber Frame Counter */
458 u32 tfcs; /* TX FCS Error Counter */
459 u32 txcf; /* TX Control Frame Counter */
460 u32 tovr; /* TX Oversize Frame Counter */
461 u32 tund; /* TX Undersize Frame Counter */
462 u32 tfrg; /* TX Fragments Frame Counter */
1351 u32 a0txcr; /* Port Arbitration 0 Tx CR */
1352 u32 a1txcr; /* Port Arbitration 1 Tx CR */
1353 u32 a2txcr; /* Port Arbitration 2 Tx CR */
1354 u32 mreqtxbacr[3]; /* Port Request Tx Buffer ACR */
1355 u32 mrspfctxbacr; /* Port Response/Flow Control Tx Buffer ACR */
2583 u32 srdstcalcr; /* 0x90 TX Calibration Control */
2642 u32 srdstcalcr; /* TX Calibration Control */
2666 u32 tecr0; /* TX Equalization Control Reg 0 */
