Lines Matching defs:pllcr0
632 u32 fcap, dcbias, bcap, pllcr1, pllcr0;
637 clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
645 setbits_be32(&srds_regs->bank[pll_num].pllcr0,
663 clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
671 setbits_be32(&srds_regs->bank[pll_num].pllcr0,
697 clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
699 pllcr0 = (in_be32
700 (&srds_regs->bank[pll_num].pllcr0)|
702 out_be32(&srds_regs->bank[pll_num].pllcr0,
703 pllcr0);
725 clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
727 pllcr0 = (in_be32(&srds_regs->bank[pll_num].pllcr0)|
729 out_be32(&srds_regs->bank[pll_num].pllcr0,
730 pllcr0);
1179 u32 pllcr0 = srds_regs->bank[i].pllcr0;
1180 u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
