Lines Matching refs:srds_regs
596 static int calibrate_pll(serdes_corenet_t *srds_regs, int pll_num)
604 clrbits_be32(&srds_regs->bank[pll_num].rstctl,
607 clrbits_be32(&srds_regs->bank[pll_num].rstctl,
610 setbits_be32(&srds_regs->bank[pll_num].rstctl,
612 setbits_be32(&srds_regs->bank[pll_num].rstctl,
619 rst_err = in_be32(&srds_regs->bank[pll_num].rstctl) &
629 static int check_pll_locks(serdes_corenet_t *srds_regs, int pll_num)
634 if (calibrate_pll(srds_regs, pll_num)) {
637 clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
639 fcap = in_be32(&srds_regs->bank[pll_num].pllsr2) &
642 bcap = in_be32(&srds_regs->bank[pll_num].pllsr2) &
645 setbits_be32(&srds_regs->bank[pll_num].pllcr0,
647 dcbias = in_be32(&srds_regs->bank[pll_num].pllsr2) &
654 clrbits_be32(&srds_regs->bank[pll_num].rstctl,
657 clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
659 setbits_be32(&srds_regs->bank[pll_num].pllcr1,
661 if (calibrate_pll(srds_regs, pll_num)) {
663 clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
665 fcap = in_be32(&srds_regs->bank[pll_num].pllsr2)
668 bcap = in_be32(&srds_regs->bank[pll_num].pllsr2)
671 setbits_be32(&srds_regs->bank[pll_num].pllcr0,
674 (&srds_regs->bank[pll_num].pllsr2) &
679 srds_regs->bank[pll_num].rstctl,
682 setbits_be32(&srds_regs->bank[pll_num].pllcr1,
684 clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
686 setbits_be32(&srds_regs->bank[pll_num].pllcr1,
690 clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
693 (&srds_regs->bank[pll_num].pllcr1)|
695 out_be32(&srds_regs->bank[pll_num].pllcr1,
697 clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
700 (&srds_regs->bank[pll_num].pllcr0)|
702 out_be32(&srds_regs->bank[pll_num].pllcr0,
704 ret = calibrate_pll(srds_regs, pll_num);
711 clrbits_be32(&srds_regs->bank[pll_num].rstctl,
717 setbits_be32(&srds_regs->bank[pll_num].pllcr1,
719 clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
721 pllcr1 = (in_be32(&srds_regs->bank[pll_num].pllcr1)|
723 out_be32(&srds_regs->bank[pll_num].pllcr1,
725 clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
727 pllcr0 = (in_be32(&srds_regs->bank[pll_num].pllcr0)|
729 out_be32(&srds_regs->bank[pll_num].pllcr0,
731 clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
733 setbits_be32(&srds_regs->bank[pll_num].pllcr1,
735 ret = calibrate_pll(srds_regs, pll_num);
775 serdes_corenet_t *srds_regs =
876 clrbits_be32(&srds_regs->bank[i].rstctl,
879 clrbits_be32(&srds_regs->bank[i].rstctl,
882 setbits_be32(&srds_regs->bank[i].rstctl,
884 setbits_be32(&srds_regs->bank[i].rstctl,
1158 serdes_corenet_t *srds_regs =
1179 u32 pllcr0 = srds_regs->bank[i].pllcr0;
