Lines Matching refs:ddr
40 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
41 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
44 out_be32(&im->ddr.cs_config[1], 0);
46 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
47 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
48 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
49 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
50 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
52 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
53 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
54 out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
55 out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
57 out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
60 /* enable DDR controller */
61 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
75 /* DDR SDRAM */
78 /* return total bus SDRAM size(bytes) -- DDR */
