Lines Matching refs:im
47 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
50 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
51 im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
52 im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
63 im->ddr.csbnds[0].csbnds =
67 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
70 im->ddr.cs_config[1] = 0;
72 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
73 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
74 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
75 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
76 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
79 if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
80 im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG | SDRAM_CFG_BI;
83 im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG;
85 im->ddr.sdram_cfg2 = CONFIG_SYS_SDRAM_CFG2;
86 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
87 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE_2;
89 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
93 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
101 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
102 volatile fsl_lbc_t *lbc = &im->im_lbc;
105 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
117 if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
