Lines Matching refs:im
52 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
55 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
59 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
89 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
94 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
95 im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
101 im->ddr.csbnds[2].csbnds = CONFIG_SYS_DDR_CS2_BNDS;
102 im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
103 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
104 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
105 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
106 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
107 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
108 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
109 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
110 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
111 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
112 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
118 im->ddr.csbnds[2].csbnds =
122 im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
125 im->ddr.cs_config[0] = 0;
126 im->ddr.cs_config[1] = 0;
127 im->ddr.cs_config[3] = 0;
129 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
130 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
132 im->ddr.sdram_cfg =
140 im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
142 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
144 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
149 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
