Lines Matching refs:im
65 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
75 clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
76 clrsetbits_be32(&im->sysconf.sicrh, SICRH_GPIO2_E | SICRH_SPI,
88 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
89 u32 rcwh = in_be32(&im->reset.rcwh);
187 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
188 u32 rcwh = in_be32(&im->reset.rcwh);
222 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
225 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
251 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
255 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
256 im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
261 im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
264 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
267 im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
268 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
271 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
272 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
273 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
274 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
275 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
276 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
277 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
278 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
279 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
283 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
298 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
305 if ((in_be32(&im->reset.rcwh) & rcw_mask) != rcw_mask)
